A 1.8V 6-bit 1GS/s 60mW CMOS folding/interpolation ADC using folder reduction circuit and auto switching encoder

Junho Moon, Heewon Kang, Daeyoon Kim, Seungjin Yeo, Dubok Lee, Minkyu Song. A 1.8V 6-bit 1GS/s 60mW CMOS folding/interpolation ADC using folder reduction circuit and auto switching encoder. In 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julien's, Malta, August 31 2008-September 3, 2008. pages 638-641, IEEE, 2008. [doi]

Abstract

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