Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny. Corrections to Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect [May 10 689-696]. IEEE Trans. VLSI Syst., 18(8):1262, 2010. [doi]
Abstract is missing.