A 0.3-V Operating, ::::V::::::th::-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond

Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Kentaro Kawakami, Junichi Miyakoshi, Shinji Mikami, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto. A 0.3-V Operating, ::::V::::::th::-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond. IEICE Transactions, 89-A(12):3634-3641, 2006. [doi]

@article{MoritaFNKMMNKY06,
  title = {A 0.3-V Operating, ::::V::::::th::-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond},
  author = {Yasuhiro Morita and Hidehiro Fujiwara and Hiroki Noguchi and Kentaro Kawakami and Junichi Miyakoshi and Shinji Mikami and Koji Nii and Hiroshi Kawaguchi and Masahiko Yoshimoto},
  year = {2006},
  doi = {10.1093/ietfec/e89-a.12.3634},
  url = {http://dx.doi.org/10.1093/ietfec/e89-a.12.3634},
  tags = {Meta-Environment},
  researchr = {https://researchr.org/publication/MoritaFNKMMNKY06},
  cites = {0},
  citedby = {0},
  journal = {IEICE Transactions},
  volume = {89-A},
  number = {12},
  pages = {3634-3641},
}