Design of Low Voltage Tunneling-FET Logic Circuits Considering Asymmetric Conduction Characteristics

Daniel H. Morris, Uygar E. Avci, Rafael Rios, Ian A. Young. Design of Low Voltage Tunneling-FET Logic Circuits Considering Asymmetric Conduction Characteristics. IEEE J. Emerg. Sel. Topics Circuits Syst., 4(4):380-388, 2014. [doi]

@article{MorrisARY14,
  title = {Design of Low Voltage Tunneling-FET Logic Circuits Considering Asymmetric Conduction Characteristics},
  author = {Daniel H. Morris and Uygar E. Avci and Rafael Rios and Ian A. Young},
  year = {2014},
  doi = {10.1109/JETCAS.2014.2361054},
  url = {http://dx.doi.org/10.1109/JETCAS.2014.2361054},
  researchr = {https://researchr.org/publication/MorrisARY14},
  cites = {0},
  citedby = {0},
  journal = {IEEE J. Emerg. Sel. Topics Circuits Syst.},
  volume = {4},
  number = {4},
  pages = {380-388},
}