System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation - researchr publication authors

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Moaz Mostafa, Mona Safar, M. Watheq El-Kharashi, Mohamed Dessouky. System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation. In 15th International Microprocessor Test and Verification Workshop, MTV 2014, Austin, TX, USA, December 15-16, 2014. pages 55-60, IEEE, 2014. [doi]

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