Moaz Mostafa, Mona Safar, M. Watheq El-Kharashi, Mohamed Dessouky. System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation. In 15th International Microprocessor Test and Verification Workshop, MTV 2014, Austin, TX, USA, December 15-16, 2014. pages 55-60, IEEE, 2014. [doi]
@inproceedings{MostafaSED14,
title = {System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation},
author = {Moaz Mostafa and Mona Safar and M. Watheq El-Kharashi and Mohamed Dessouky},
year = {2014},
doi = {10.1109/MTV.2014.23},
url = {http://dx.doi.org/10.1109/MTV.2014.23},
researchr = {https://researchr.org/publication/MostafaSED14},
cites = {0},
citedby = {0},
pages = {55-60},
booktitle = {15th International Microprocessor Test and Verification Workshop, MTV 2014, Austin, TX, USA, December 15-16, 2014},
publisher = {IEEE},
isbn = {978-1-4673-6858-2},
}