Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis. Reducing power, area, and delay of threshold logic gates considering non-integer weights. In IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017. pages 1-4, IEEE, 2017. [doi]
Abstract is missing.