Low Power Low Latency Floorplan‐aware Path Synthesis in Application-Specific Network-on-Chip Design

Priyajit Mukherjee, Santanu Chattopadhyay. Low Power Low Latency Floorplan‐aware Path Synthesis in Application-Specific Network-on-Chip Design. Integration, 58:167-188, 2017. [doi]

Abstract

Abstract is missing.