The design and implementation of a low-latency on-chip network

Robert D. Mullins, Andrew West, Simon W. Moore. The design and implementation of a low-latency on-chip network. In Fumiyasu Hirose, editor, Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006. pages 164-169, IEEE, 2006. [doi]

@inproceedings{MullinsWM06,
  title = {The design and implementation of a low-latency on-chip network},
  author = {Robert D. Mullins and Andrew West and Simon W. Moore},
  year = {2006},
  doi = {10.1145/1118299.1118348},
  url = {http://doi.acm.org/10.1145/1118299.1118348},
  tags = {design},
  researchr = {https://researchr.org/publication/MullinsWM06},
  cites = {0},
  citedby = {0},
  pages = {164-169},
  booktitle = {Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006},
  editor = {Fumiyasu Hirose},
  publisher = {IEEE},
  isbn = {0-7803-9451-8},
}