The following publications are possibly variants of this publication:
- Area and throughput optimized ASIP for multi-standard turbo decodingRachid Al-Khayat, Purushotham Murugappa, Amer Baghdadi, Michel Jézéquel. rsp 2011: 79-84 [doi]
- 2 multi-standard turbo decoderRachid Al-Khayat, Amer Baghdadi, Michel Jézéquel. issoc 2012: 1-7 [doi]
- A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP contextVianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet, Jean-Noel Bazin, Michael Hübner. isvlsi 2013: 40-45 [doi]
- An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architectureVianney Lapotre, Michael Hübner, Guy Gogniat, Purushotham Murugappa, Amer Baghdadi, Jean-Philippe Diguet. recosoc 2013: 1-8 [doi]
- FPGA prototyping and performance evaluation of multi-standard Turbo/LDPC Encoding and DecodingPurushotham Murugappa, Jean-Noel Bazin, Amer Baghdadi, Michel Jézéquel. rsp 2012: 143-148 [doi]