POSET timing and its application to the synthesis and verification of gate-level timed circuits

Chris J. Myers, Tomas Rokicki, Teresa H. Y. Meng. POSET timing and its application to the synthesis and verification of gate-level timed circuits. IEEE Trans. on CAD of Integrated Circuits and Systems, 18(6):769-786, 1999. [doi]

Authors

Chris J. Myers

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Tomas Rokicki

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Teresa H. Y. Meng

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