Chris J. Myers, Tomas Rokicki, Teresa H. Y. Meng. POSET timing and its application to the synthesis and verification of gate-level timed circuits. IEEE Trans. on CAD of Integrated Circuits and Systems, 18(6):769-786, 1999. [doi]
@article{MyersRM99,
title = {POSET timing and its application to the synthesis and verification of gate-level timed circuits},
author = {Chris J. Myers and Tomas Rokicki and Teresa H. Y. Meng},
year = {1999},
doi = {10.1109/43.766727},
url = {http://doi.ieeecomputersociety.org/10.1109/43.766727},
researchr = {https://researchr.org/publication/MyersRM99},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {18},
number = {6},
pages = {769-786},
}