Specification, Planning, and Synthesis in a VHDL Design Environment

Vijay Nagasamy, Neerav Berry, Carlos Dangelo. Specification, Planning, and Synthesis in a VHDL Design Environment. IEEE Design & Test of Computers, 9(2):58-68, 1992. [doi]

Authors

Vijay Nagasamy

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Neerav Berry

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Carlos Dangelo

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