A 8-ns Settling Time Fully Integrated LDO with Dynamic Biasing and Bulk Modulation Techniques in 40nm CMOS

T. Nagateja, Neha Kumari, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai. A 8-ns Settling Time Fully Integrated LDO with Dynamic Biasing and Bulk Modulation Techniques in 40nm CMOS. In IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020. pages 1-4, IEEE, 2020. [doi]

Abstract

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