Compensating Algorithmic-Loop Performance Degradation in Asynchronous Circuits Using Hardware Multi-threading

Mehrdad Najibi, Hossein Pedram. Compensating Algorithmic-Loop Performance Degradation in Asynchronous Circuits Using Hardware Multi-threading. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France. pages 507-510, IEEE Computer Society, 2008. [doi]

Authors

Mehrdad Najibi

This author has not been identified. Look up 'Mehrdad Najibi' in Google

Hossein Pedram

This author has not been identified. Look up 'Hossein Pedram' in Google