Design and evaluation of variable stages pipeline processor chip

Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo. Design and evaluation of variable stages pipeline processor chip. In Proceedings of the 16th Asia South Pacific Design Automation Conference, ASP-DAC 2011, Yokohama, Japan, January 25-27, 2011. pages 95-96, IEEE, 2011. [doi]

@inproceedings{NakabayashiSOK11,
  title = {Design and evaluation of variable stages pipeline processor chip},
  author = {Tomoyuki Nakabayashi and Takahiro Sasaki and Kazuhiko Ohno and Toshio Kondo},
  year = {2011},
  doi = {10.1109/ASPDAC.2011.5722314},
  url = {http://dx.doi.org/10.1109/ASPDAC.2011.5722314},
  tags = {design},
  researchr = {https://researchr.org/publication/NakabayashiSOK11},
  cites = {0},
  citedby = {0},
  pages = {95-96},
  booktitle = {Proceedings of the 16th Asia South Pacific Design Automation Conference, ASP-DAC 2011, Yokohama, Japan, January 25-27, 2011},
  publisher = {IEEE},
  isbn = {978-1-4244-7516-2},
}