The following publications are possibly variants of this publication:
- Design and Evaluation of Variable Stages Pipeline Processor ChipTomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo. isia 2011: 220-226 [doi]
- Design and evaluation of variable stages pipeline processor with low-energy techniquesT. Nakabayashi, T. Sasaki, I. K. Ohno, T. Kondo. iet-cdt, 6(1):43-49, 2012. [doi]
- Energy Optimization using Fine-Grain Variable Stages Pipeline Processor ChipTomoyuki Nakabayashi, Takahiro Sasaki, Hitoshi Nakamura, Kazuhiko Ohno, Toshio Kondo. ijnc, 3(2):192-204, 2013. [doi]
- Design and evaluation of fine-grain-mode transition method based on dynamic memory access analysing for variable stages pipeline processorTakahiro Sasaki, Tomoyuki Nakabayashi, Kazumasa Nomura, Kazuhiko Ohno, Toshio Kondo. iet-cdt, 7(1):41-47, 2013. [doi]