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Masami Nakajima, Michitaka Kameyama. Design of Multiple-Valued Linear Digital Circuits for Highly Parallel Unary Operations. In ISMVL. pages 283-288, 1993.
Possibly Related PublicationsThe following publications are possibly variants of this publication: Design of Multiple-Valued Linear Digital Circuits for Highly Parallel ::::k::::-Ary OperationsMasami Nakajima, Michitaka Kameyama. ismvl 1994: 223-230 Design of a Highly Parallel Multiple-Valued Linear Digital System for k-Ary Operations Based on Extended Representation MatricesM. Ryu, Michitaka Kameyama. ismvl 1995: 20 [doi] Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level RedundancyMasami Nakajima, Michitaka Kameyama. ismvl 1996: 104-109 [doi]
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