A 40nm Embedded SG-MONOS Flash Macro for High-end MCU Achieving 200MHz Random Read Operation and 7.91Mb/mm2 Density with Charge Assisted Offset Cancellation Sense Amplifier

Masaya Nakano, Yoshinobu Kaneda, Koichi Takeda, Takahiro Shimoi, Yasunobu Aoki, Satoru Nakanishi, Yosuke Tashiro, Yasuhiko Taito, Ken Matsubara, Munekatsu Nakagawa, Tomoya Ogawa, Takashi Kurafuji, Hidenori Mitani, Takashi Ito, Takashi Kono. A 40nm Embedded SG-MONOS Flash Macro for High-end MCU Achieving 200MHz Random Read Operation and 7.91Mb/mm2 Density with Charge Assisted Offset Cancellation Sense Amplifier. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2021, Busan, Korea, Republic of, November 7-10, 2021. pages 1-3, IEEE, 2021. [doi]

Authors

Masaya Nakano

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Yoshinobu Kaneda

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Koichi Takeda

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Takahiro Shimoi

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Yasunobu Aoki

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Satoru Nakanishi

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Yosuke Tashiro

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Yasuhiko Taito

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Ken Matsubara

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Munekatsu Nakagawa

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Tomoya Ogawa

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Takashi Kurafuji

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Hidenori Mitani

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Takashi Ito

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Takashi Kono

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