Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto. A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement. In Fifteenth International Symposium on Quality Electronic Design, ISQED 2014, Santa Clara, CA, USA, March 3-5, 2014. pages 16-23, IEEE, 2014. [doi]
@inproceedings{NakataKOJSTNNYFNKKY14,
title = {A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement},
author = {Yohei Nakata and Yuta Kimi and Shunsuke Okumura and Jinwook Jung and Takuya Sawada and Taku Toshikawa and Makoto Nagata and Hirofumi Nakano and Makoto Yabuuchi and Hidehiro Fujiwara and Koji Nii and Hiroyuki Kawai and Hiroshi Kawaguchi and Masahiko Yoshimoto},
year = {2014},
doi = {10.1109/ISQED.2014.6783301},
url = {http://dx.doi.org/10.1109/ISQED.2014.6783301},
researchr = {https://researchr.org/publication/NakataKOJSTNNYFNKKY14},
cites = {0},
citedby = {0},
pages = {16-23},
booktitle = {Fifteenth International Symposium on Quality Electronic Design, ISQED 2014, Santa Clara, CA, USA, March 3-5, 2014},
publisher = {IEEE},
}