Taku Toshikawa - researchr alias

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Viewing Publication 1 - 5 from 5

2018

An ultra-wide range (0.01-240 Gbps) transmitter with latched AC-coupled driver and dummy data transient generatorTsuyoshi Ebuchi, Taku Toshikawa, Seiji Watanabe, Yutaka Terada, Toru Iwata. ieiceee, 15(3):20171151, 2018. [doi]

2014

A jitter suppression technique against data pattern dependency on high-speed interfaces for highly integrated SoCsTsuyoshi Ebuchi, Taku Toshikawa, Seiji Watanabe, Tomohiro Tsuchiya, Yutaka Terada, Tomoko Chiba, Keijiro Umehara, Toru Iwata, Takefumi Yoshikawa. ieiceee, 11(22):20140949, 2014. [doi]

A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvementYohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto. isqed 2014: 16-23 [doi]

A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage FluctuationYohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto. ieicet, 97-C(4):332-341, 2014. [doi]

2012

Evaluation of SRAM-Core Susceptibility against Power Supply Voltage VariationTakuya Sawada, Taku Toshikawa, Kumpei Yoshikawa, Hidehiro Takata, Koji Nii, Makoto Nagata. ieicet, 95-C(4):586-593, 2012. [doi]

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