0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM - researchr publication authors

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Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto. 0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM. In Vojin G. Oklobdzija, Barry Pangle, Naehyuck Chang, Naresh R. Shanbhag, Chris H. Kim, editors, Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010. pages 219-224, ACM, 2010. [doi]

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