Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto. 0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM. In Vojin G. Oklobdzija, Barry Pangle, Naehyuck Chang, Naresh R. Shanbhag, Chris H. Kim, editors, Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010. pages 219-224, ACM, 2010. [doi]
@inproceedings{NakataOKY10,
title = {0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM},
author = {Yohei Nakata and Shunsuke Okumura and Hiroshi Kawaguchi and Masahiko Yoshimoto},
year = {2010},
doi = {10.1145/1840845.1840888},
url = {http://doi.acm.org/10.1145/1840845.1840888},
tags = {caching, architecture, context-aware},
researchr = {https://researchr.org/publication/NakataOKY10},
cites = {0},
citedby = {0},
pages = {219-224},
booktitle = {Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010},
editor = {Vojin G. Oklobdzija and Barry Pangle and Naehyuck Chang and Naresh R. Shanbhag and Chris H. Kim},
publisher = {ACM},
isbn = {978-1-4503-0146-6},
}