A 16nm 0.67pJ/bit 80Mb/s Circuit-System Co-Optimized Time Domain Brain Channel Receiver

Harshit Naman, Gourab Barik, Sarthak Antal, Samyadip Sarkar, Ming-Che Li, Shreyas Sen. A 16nm 0.67pJ/bit 80Mb/s Circuit-System Co-Optimized Time Domain Brain Channel Receiver. In IEEE Custom Integrated Circuits Conference, CICC 2026, Seattle, WA, USA, April 19-23, 2026. pages 1-4, IEEE, 2026. [doi]

Abstract

Abstract is missing.