The following publications are possibly variants of this publication:
- A high speed word level finite field multiplier using reordered normal basisAshkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmadi. iscas 2008: 3278-3281 [doi]
- A Word-Level Finite Field Multiplier Using Normal BasisAshkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmadi. TC, 60(6):890-895, 2011. [doi]
- Efficient VLSI Implementation of a Sequential Finite Field Multiplier Using Reordered Normal Basis in Domino LogicParham Hosseinzadeh Namin, Crystal Roma, Roberto Muscedere, Majid Ahmadi. tvlsi, 26(11):2542-2552, 2018. [doi]
- High-speed hardware implementation of a serial-in parallel-out finite field multiplier using reordered normal basisAshkan Hosseinzadeh Namin, Karl Leboeuf, Roberto Muscedere, Huapeng Wu, Majid Ahmadi. iet-cds, 4(2):168-179, 2010. [doi]
- Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring TechniqueShoaleh Hashemi Namin, Huapeng Wu, Majid Ahmadi. tvlsi, 25(2):441-449, 2017. [doi]