Continuous-Time ΔΣ Modulators With Improved Linearity and Reduced Clock Jitter Sensitivity Using the Switched-Capacitor Return-to-Zero DAC

Timir Nandi, Karthikeya Boominathan, Shanthi Pavan. Continuous-Time ΔΣ Modulators With Improved Linearity and Reduced Clock Jitter Sensitivity Using the Switched-Capacitor Return-to-Zero DAC. J. Solid-State Circuits, 48(8):1795-1805, 2013. [doi]

@article{NandiBP13,
  title = {Continuous-Time ΔΣ Modulators With Improved Linearity and Reduced Clock Jitter Sensitivity Using the Switched-Capacitor Return-to-Zero DAC},
  author = {Timir Nandi and Karthikeya Boominathan and Shanthi Pavan},
  year = {2013},
  doi = {10.1109/JSSC.2013.2259012},
  url = {http://dx.doi.org/10.1109/JSSC.2013.2259012},
  researchr = {https://researchr.org/publication/NandiBP13},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {48},
  number = {8},
  pages = {1795-1805},
}