Siva Narendra. Challenges and design choices in nanoscale CMOS. JETC, 1(1):7-49, 2005. [doi]
@article{Narendra05,
title = {Challenges and design choices in nanoscale CMOS},
author = {Siva Narendra},
year = {2005},
doi = {10.1145/1063803.1063805},
url = {http://doi.acm.org/10.1145/1063803.1063805},
tags = {design},
researchr = {https://researchr.org/publication/Narendra05},
cites = {0},
citedby = {0},
journal = {JETC},
volume = {1},
number = {1},
pages = {7-49},
}