A Methodology for Worst-Case Analysis of Integrated Circuits

Sani R. Nassif, Andrzej J. Strojwas, Stephen W. Director. A Methodology for Worst-Case Analysis of Integrated Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems, 5(1):104-113, 1986. [doi]

@article{NassifSD86,
  title = {A Methodology for Worst-Case Analysis of Integrated Circuits},
  author = {Sani R. Nassif and Andrzej J. Strojwas and Stephen W. Director},
  year = {1986},
  url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=28435&arnumber=1270181&count=21&index=9},
  tags = {analysis},
  researchr = {https://researchr.org/publication/NassifSD86},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
  volume = {5},
  number = {1},
  pages = {104-113},
}