A Scalable Circuit-Architecture Co-Design to Improve Memory Yield for High-Performance Processors

Patrick Ndai, Ashish Goel, Kaushik Roy. A Scalable Circuit-Architecture Co-Design to Improve Memory Yield for High-Performance Processors. IEEE Trans. VLSI Syst., 18(8):1209-1219, 2010. [doi]

Authors

Patrick Ndai

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Ashish Goel

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Kaushik Roy

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