FPGA Based Implementation of High Performance Architectural Level Low Power 32-bit RISC Core - researchr publication authors

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Joseph Neenu, S. Sabarinath, K. Sankarapandiammal. FPGA Based Implementation of High Performance Architectural Level Low Power 32-bit RISC Core. In ARTCom 2009, International Conference on Advances in Recent Technologies in Communication and Computing, Kottayam, Kerala, India, 27-28 October 2009. pages 53-57, IEEE Computer Society, 2009. [doi]

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