Joseph Neenu, S. Sabarinath, K. Sankarapandiammal. FPGA Based Implementation of High Performance Architectural Level Low Power 32-bit RISC Core. In ARTCom 2009, International Conference on Advances in Recent Technologies in Communication and Computing, Kottayam, Kerala, India, 27-28 October 2009. pages 53-57, IEEE Computer Society, 2009. [doi]
@inproceedings{NeenuSS09,
title = {FPGA Based Implementation of High Performance Architectural Level Low Power 32-bit RISC Core},
author = {Joseph Neenu and S. Sabarinath and K. Sankarapandiammal},
year = {2009},
doi = {10.1109/ARTCom.2009.230},
url = {http://doi.ieeecomputersociety.org/10.1109/ARTCom.2009.230},
tags = {architecture},
researchr = {https://researchr.org/publication/NeenuSS09},
cites = {0},
citedby = {0},
pages = {53-57},
booktitle = {ARTCom 2009, International Conference on Advances in Recent Technologies in Communication and Computing, Kottayam, Kerala, India, 27-28 October 2009},
publisher = {IEEE Computer Society},
isbn = {978-0-7695-3845-7},
}