Mohammad Hossein Neishaburi, Zeljko Zilic. A Fault Tolerant Hierarchical Network on Chip Router Architecture. J. Electronic Testing, 29(4):485-497, 2013. [doi]
@article{NeishaburiZ13,
title = {A Fault Tolerant Hierarchical Network on Chip Router Architecture},
author = {Mohammad Hossein Neishaburi and Zeljko Zilic},
year = {2013},
doi = {10.1007/s10836-013-5398-4},
url = {http://dx.doi.org/10.1007/s10836-013-5398-4},
researchr = {https://researchr.org/publication/NeishaburiZ13},
cites = {0},
citedby = {0},
journal = {J. Electronic Testing},
volume = {29},
number = {4},
pages = {485-497},
}