Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits

Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda. Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems, 26(3):592-605, 2007. [doi]

Abstract

Abstract is missing.