Power-Down Mode Verification for Hierarchical Analog Circuits - researchr publication authors

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Maximilian Neuner, Helmut Graeb. Power-Down Mode Verification for Hierarchical Analog Circuits. In 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019, Lausanne, Switzerland, July 15-18, 2019. pages 125-128, IEEE, 2019. [doi]

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