Maximilian Neuner, Helmut Graeb. Power-Down Mode Verification for Hierarchical Analog Circuits. In 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019, Lausanne, Switzerland, July 15-18, 2019. pages 125-128, IEEE, 2019. [doi]
@inproceedings{NeunerG19,
title = {Power-Down Mode Verification for Hierarchical Analog Circuits},
author = {Maximilian Neuner and Helmut Graeb},
year = {2019},
doi = {10.1109/SMACD.2019.8795264},
url = {https://doi.org/10.1109/SMACD.2019.8795264},
researchr = {https://researchr.org/publication/NeunerG19},
cites = {0},
citedby = {0},
pages = {125-128},
booktitle = {16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019, Lausanne, Switzerland, July 15-18, 2019},
publisher = {IEEE},
isbn = {978-1-7281-1201-5},
}