Logic Synthesis and Verification of the CPU and Caches of a Mainframe System - researchr publication authors

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Huy Nam Nguyen, J. P. Tual, L. Ducousso, M. Thill, P. Vallet. Logic Synthesis and Verification of the CPU and Caches of a Mainframe System. In Robert Werner, editor, EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28 - March 3, 1994, Paris, France. pages 60-64, IEEE Computer Society, 1994.

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