Huy Nam Nguyen, J. P. Tual, L. Ducousso, M. Thill, P. Vallet. Logic Synthesis and Verification of the CPU and Caches of a Mainframe System. In Robert Werner, editor, EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28 - March 3, 1994, Paris, France. pages 60-64, IEEE Computer Society, 1994.
@inproceedings{NguyenTDTV94,
title = {Logic Synthesis and Verification of the CPU and Caches of a Mainframe System},
author = {Huy Nam Nguyen and J. P. Tual and L. Ducousso and M. Thill and P. Vallet},
year = {1994},
tags = {caching, logic},
researchr = {https://researchr.org/publication/NguyenTDTV94},
cites = {0},
citedby = {0},
pages = {60-64},
booktitle = {EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28 - March 3, 1994, Paris, France},
editor = {Robert Werner},
publisher = {IEEE Computer Society},
isbn = {0-8186-5410-4},
}