Meng Ni, Fule Li, Weitao Li, Chun Zhang, Zhihua Wang. A high-speed analog front-end circuit used in a 12bit 1GSps pipeline ADC. In 2015 IEEE 11th International Conference on ASIC, ASICON 2015, Chengdu, China, November 3-6, 2015. pages 1-4, IEEE, 2015. [doi]
Abstract is missing.