Abstract is missing.
- Waveform base clock tree delay analysis using parallel processingGoro Suzuki. 1-5 [doi]
- A physical model of novel UV and blue-extended photodetector based on CMOS processXiangliang Jin, Manfang Tian, Zhenyu Jiang, Han Wang. 1-4 [doi]
- Improvement of the charge pump for Maneatis PLLsZhan Shi, Zhenan Tang, Fan Yang, Jiarui Wu. 1-3 [doi]
- Exploring stacked main memory architecture for 3D GPGPUsYuang Zhang, Li Li, Axel Jantsch, Zhonghai Lu, Minglun Gao, Yuxiang Fu, Hongbing Pan. 1-4 [doi]
- Challenges in the design of self-powered wearable wireless sensors for healthcare Internet-of-ThingsYong Lian. 1-4 [doi]
- A high-speed analog front-end circuit used in a 12bit 1GSps pipeline ADCMeng Ni, Fule Li, Weitao Li, Chun Zhang, Zhihua Wang. 1-4 [doi]
- A hall sensor microsystem for current measurement used in watt-hour meterWenhao Xu, Xunhua Guo, Jinling Chen, Guoxing Wang. 1-4 [doi]
- 3D resist modeling for OPC correction and verificationLiang Zhu, Qian Ren, Neo Tan, Zhibo Ai. 1-4 [doi]
- Design and implementation of a body monitoring baseband system for human body communicationXiaofei Chen, Bo Wang, Ke Lin, Ning Li, Chen Chen, Haibin Shao, Xin'an Wang. 1-4 [doi]
- Adaptive semiblind background calibration of timing mismatches in an M-channel time-interleaved analog-to-digital converterSujuan Liu, Haixiao Ma, Jiashuai Cui. 1-4 [doi]
- An overview of soft-switching technique for flyback convertersXiaofei Chen, Xiaorui Liu, Yingjie Zhang, Xuecheng Zou, Shuangxi Lin. 1-4 [doi]
- A PVT-insensitive all digital CMOS time-to-digital converter based on looped delay-line with extension schemeSiliang Hua, Donghui Wang, Leiou Wang, Yan Liu, Jiarui Li. 1-4 [doi]
- PDK design of 0.13um SOI processJiang Bingjian, Junli Sheng, Zhangwen Tang. 1-4 [doi]
- I/Q imbalance estimation in OFDM systemsXuerong Zhou, Xiangyan Xue, Fan Ye 0001, Junyan Ren. 1-4 [doi]
- 2.4/5.5GHz LNA switch designs based on high resistive substrate 0.35um SiGe BiCMOSChaojiang Li, Xiaoxia Wang, Vibhor Jain, Hanyi Ding, Myra Boenke, Dawn Wang, Randy Wolf, Alvin Joseph. 1-4 [doi]
- An all-digital quadrature RF transmitter with 8-bit ΣΔ modulationPan Xue, Yilei Shen, Yang Zhao, Zhiliang Hong. 1-4 [doi]
- An input-powered 1.1-μA Iq 13.56 MHz RF energy harvesting system for biomedical implantable devicesJames Davis 0009, Joseph Sankman, Dongsheng Ma. 1-4 [doi]
- D-band down conversion chipset with I-Q outputs using 0.13μm SiGe BiCMOS technologyXiaodong Deng, Yihu Li, Wen Wu, Yong-Zhong Xiong. 1-4 [doi]
- Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS cachesPei-Yuan Chou, I-Chen Wu, Jai-Wei Lin, Xuan-Yu Lin, Tien-Fu Chen, Tay-Jyi Lin, Jinn-Shyan Wang. 1-4 [doi]
- A quenching-and-reset circuit with programmable hold-off time for single photon avalanche diodes in 0.18μm CMOSJinglin Huang, Qi Zhang, Li Tian, Hui Wang, Songlin Feng. 1-4 [doi]
- Photoelectrochemically recessed AlGaN/GaN monolithic inverter incorporating LiNbO3 ferroelectric filmChing-Ting Lee, Jhe-Hao Chang, Chun-Yen Tseng. 1-4 [doi]
- A SIMD multiplier-accumulator design for pairing cryptographyWeizhen Wang, Jun Han 0003, Jielin Wang, Xiaoyang Zeng. 1-4 [doi]
- Influence of substrate coupling noise to clock and data recoveryYongsheng Wang, Min Wang, Huaixin Xian, Yunfei Du, Bei Cao, Xiaowei Liu. 1-4 [doi]
- An adaptive voltage scaling circuit based on dominate pole compensationPing Luo, Songlin Fu, Xiang Zhang, Yi Bao, Dongjun Wang. 1-4 [doi]
- A thermal-aware distribution method of TSV in 3D ICLigang Hou, Jingyan Fu, Jinhui Wang, Na Gong, Wei Zhao 0001, Shuqin Geng. 1-3 [doi]
- A 28-Gb/s 60-GHz wireless transceiver in 65nm CMOS with 64QAM capabilityKenichi Okada. 1-4 [doi]
- A 16-bit low-power double-sampled delta sigma modulator for audio applicationsYongsheng Wang, Hongying Wang, Fengchang Lai, Bei Cao, Yang Liu, Xiaowei Liu. 1-4 [doi]
- A 10-bit DAC with 2.9 μν low frequency noise for high performance MEMS capacitive accelerometer applicationQuan Sun, Min Qi, Yi Gu, Liang Tang, Donghai Qiao. 1-4 [doi]
- A new intrinsic parameter extraction approach for small-signal model of AlGaN/GaN devicesLinghan Zhang, Yunzhou Wang, Yicong Liu, Xusheng Tang. 1-4 [doi]
- Generation of low power testing based on novel SIC sequencesBei Cao, Zhiyuan Li, Dianzhong Wen. 1-4 [doi]
- Quantitative performance and power analysis of LTE using high level synthesisYun Liang 0001, Shuo Wang. 1-4 [doi]
- A 2-V 40-MS/s 14-bit pipelined ADC for CMOS image sensorTeng Chen, Leli Peng, Haibin Li, Ning Ding, Cheng Ma, Yuchun Chang. 1-4 [doi]
- Design of explicit-pulse generators with CNTFETWang Qian, Wang Pengjun, Gong Daohui. 1-4 [doi]
- Reusable IO technique for improved utility of IC test circuit areaJunteng Zhang, Jinhui Wang, Ligang Hou, Na Gong. 1-5 [doi]
- Simulation and analysis of P+/N SPAD for 3D imagingHongjiao Yang, Xiangliang Jin, Lizhen Tang, Weihui Liu, Jia Yang. 1-4 [doi]
- A low-leakage power clamp ESD protection circuit with prolonged ESD discharge time and compact detection networkJian Cao, Zhenxu Ye, Yuan Wang 0001, Guangyi Lu, Xing Zhang 0002. 1-4 [doi]
- A network components insertion method for 3D application-specific Network-on-ChipRongrong Zhou, Fen Ge, Gui Feng, Ning Wu. 1-4 [doi]
- A 30 nA, 6.6 ppm/°C, high PSRR subthreshold CMOS voltage referenceYongquan Li, Mei Jiang, Liangwei Cai. 1-4 [doi]
- A 125KHz low frequency power recovery circuit for battery-less TPMS SoCYi Wang, Liji Wu, Zhi-Yuan Tu, Xiangmin Zhang, Wen Jia. 1-4 [doi]
- Iterative optimization algorithm for sound localizationFang Sun, Jin-mei Lai. 1-4 [doi]
- An automatic software/hardware verification platform prototype for reconfigurable audio algorithm in media SoCZheng Zheng, Xin'an Wang, Zhaoyang Guo, Guoxing Zhang. 1-4 [doi]
- Efficient early termination schemes for belief-propagation decoding of polar codesYuanrui Ren, Chuan Zhang, Xing Liu, Xiaohu You. 1-4 [doi]
- An inductive wireless telemetry circuit with OOK modulation for implantable cardiac pacemakersChong Guo, Hong Zhang 0009, Zhouyi Ma, Jie Zhang 0039, Jie Lin, Ruizhi Zhang. 1-4 [doi]
- A 10-bit 40 MS/s successive approximation register analog-to-digital converter with Vcm-based method for wireless communicationsWen Cheng Lai. 1-5 [doi]
- Functional coverage-driven UVM-based UART IP verificationWei Ni, Xiaotian Wang. 1-4 [doi]
- An automatic translation and parallelization system for general purpose reconfigurable processorFengshuo Tian, Weiguang Sheng, Weifeng He. 1-4 [doi]
- Flat passband gain design algorithm for 2nd-order RC polyphase filterYoshiki Niki, Shu Sasaki, Nobu Yamaguchi, Jian Kang, Takashi Kitahara, Haruo Kobayashi. 1-4 [doi]
- Ultra low power circuits design based on III-V group heterojunction tunnel field effect transistorJipan Huang, Fang Gao, Xin'an Wang, Hongying Chen. 1-4 [doi]
- A 2.4GHz low noise high linearity RF front-end designZhijian Chen, Min Cai, Ken Xu, Weiguo Zheng. 1-4 [doi]
- Design and optimization of asynchronous circuits with gate-level pipeliningMakoto Ikeda. 1-4 [doi]
- A new Schmitt trigger with adjustable hysteresis using floating-gate MOS threshold inverterGuoqiang Hang, Guoquan Zhu. 1-4 [doi]
- High performance protocol converters for two phase quasi-delay insensitive system-level communicationYao Peng, Yanfei Yang, Xiaofei Qi. 1-4 [doi]
- A 6bit 4GS/s current-steering digital-to-analog converter in 40nm CMOS with adjustable bias and DfT blockLong Zhao, Ji He, Yuhua Cheng. 1-4 [doi]
- Nanoscale register file circuit design - Challenges and opportunitiesKhawar Sarfraz, Mansun Chan. 1-4 [doi]
- An experimental study on the potential use of ReRAM as SSD bufferMengnan Wu, Yang Yang 0025, Liangliang Dai, Xinxin Zhang, Hongbin Sun 0001, Ruizhi Zhang, Jianxiao Wang, Nanning Zheng. 1-4 [doi]
- Primal-dual method based simultaneous functional unit and register bindingJianmo Ni, Cong Hao, Nan Wang 0003, Qian Ai, Takeshi Yoshimura. 1-4 [doi]
- Deep trench junction termination employing variable-K dielectric for high voltage devicesHuan Li, Xingbi Chen. 1-4 [doi]
- Cell-based programmable phase shifter design for pulsed radar SoCJinn-Yann Liu, Shi-Yu Huang, Ta-Shun Chu. 1-4 [doi]
- Impacts of external magnetic field and high temperature disturbance on MRAM reliability based on FPGA test platformKai Yang, Yanqing Zhao, Jianguo Yang, Xiaoyong Xue, Yinyin Lin, Jun-Soo Bae. 1-4 [doi]
- A SFA and I/Q mismatch auto-calibration scheme for high IRR multi-mode GPS RF receiverQin Chen, Dongpo Chen, Tingting Mo. 1-4 [doi]
- Ultra-sensitive and responsive capacitive humidity sensor based on graphene oxideQiangqiang Ye, Chenyu Wen, Ming Xu, Shi-Li Zhang, Dongping Wu. 1-4 [doi]
- CMOS image sensor with programmable compressed sensingHuixian Ye, Li Tian, Qi Zhang, Hui Wang, Songlin Feng. 1-4 [doi]
- A low-power parallel-to-serial conversion circuit for CMOS image sensorsJicun Zhang, Nan Chen 0003, Chuanming Liu, Libin Yao. 1-4 [doi]
- Improved monitoring-path selection algorithm for suspicious timing error prediction based timing speculationShinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa. 1-4 [doi]
- Low on-resistance power MOSFET design for automotive applicationsTianhong Ye, Kuan W. A. Chee. 1-4 [doi]
- A 4th-order N-path filter in 40nm CMOS with tunable Gm-C stage and reduced center-frequency offsetRundao Lu, Zhijian Lu, Dongpo Chen, Tingting Mo. 1-4 [doi]
- A fast vector reuse verification method for standard cell libraryLigang Hou, Jingsong Zhi, Lin Zhu, Jinhui Wang, Xiaohong Peng, Shuqin Geng. 1-4 [doi]
- Tunable voltage-mode four inputs universal biquad using three DVCCsJiun-Wei Horng, Tung-Hsien Chan, Toung-Yi Li. 1-4 [doi]
- Analysis and design of quickly starting crystal oscillatorWeiguo Zheng, Min Cai, Xiao-Yong He, Ken Xu, Zhijian Chen. 1-4 [doi]
- 100MS/s 9-bit 0.43mW SAR ADC with custom capacitor arrayJingjing Wang, Rongjin Xu, Chixiao Chen, Fan Ye 0001, Jun Xu, Junyan Ren. 1-4 [doi]
- A low cost readout and processing circuit for integrated CMOS geomagnetic sensorsKe Liu, Renwei Zhang, Zhankun Du, Li Shao, Xiao Ma. 1-4 [doi]
- Ultra-short length stochastic computation based on multiple partition computingJienan Chen, JianHao Hu, Jiangyun Zhou. 1-4 [doi]
- Employing the mixed FBB/RBB in the design of FinFET logic gatesTian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Yewen Ni, Dunshan Yu, Xiaole Cui. 1-4 [doi]
- A 8.1 mW 0.1∼2 GHz inductorless CMOS LNTA for software-defined radio applicationsBenqing Guo, Jun Chen, Yao Wang, Haiyan Jin, Guangjun Wen. 1-4 [doi]
- Resistive random access memory with high selectivity and ON/OFF ratio amplification sensingSung Hyun Jo, Hagop Nazarian. 1-3 [doi]
- A method of automatic sizing logic driver of 16nm Fin-FETZengFa Peng, Jianbin Zheng, Ailin Zhang. 1-5 [doi]
- Design of a dynamically reconfigurable arithmetic unit for matrix algorithmsWeijiang Wang, Yingtao Ding, Shan Cao, Xianli Zhao. 1-4 [doi]
- A 14b 1GS/s DAC with SFDR > 80 dBc across the whole nyquist band by mixed total 3-dimesional sort-and-combine and dynamic element matchingShuo Huang, Xuan Li, Xiaoyong Li. 1-4 [doi]
- A 1.2-V 7.2-μw ECG AFE with continuous time self-calibration filtersFeng Huang, Ke Lin, Fang Gao, Chen Chen, Haibin Shao, Bo Wang. 1-4 [doi]
- High-speed object detection based on a hierarchical parallel vision chipZhongxing Zhang, Jie Yang 0033, Honglong Li, Liyuan Liu, Jian Liu, Nanjian Wu. 1-4 [doi]
- A Viterbi decoder for UHF RFID digital basebandHe Wang, Xi Tan, Feng Chen, Chao Wang, Junyu Wang. 1-4 [doi]
- A 20 μW dual-channel analog front-end in 65nm CMOS for portable ECG monitoring systemShuo Li, Nan Qi, Vahid Behravan, Zhiliang Hong, Patrick Yin Chiang. 1-4 [doi]
- An enhanced decoder for multiple-bit error correcting BCH codesHupo Wei, Xiaole Cui, Qiang Zhang, Yufeng Jin. 1-4 [doi]
- OFDM synchronization implementation based on Chisel platform for 5G researchZiqiang Li, Yun Chen, Xiaoyang Zeng. 1-4 [doi]
- A 100MS/s 5bit fully digital flash ADC with standard cellsXiangyan Xue, Xuerong Zhou, Fan Ye 0001, Junyan Ren. 1-4 [doi]
- A low complexity MCMC algorithm for MIMO system with bias techniqueShuaining He, Jiangyun Zhou, JianHao Hu, Jienan Chen. 1-4 [doi]
- A 2.4 GHz two-point Δ-Σ modulator with gain calibration and AFC for WPAN/BAN applicationsChao Yang, Shaoquan Gao, Jingjing Dong, Hanjun Jiang, Woogeun Rhee, Zhihua Wang. 1-4 [doi]
- A 20MHz BW 35fJ/conv. continuous-time ΣΔ modulator with single-opamp resonator using finite GBW compensation methodZemin Feng, Jingjing Wang, Chixiao Chen, Jun Xu 0011, Junyan Ren. 1-4 [doi]
- Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementationKeita Igarashi, Masao Yanagisawa, Nozomu Togawa. 1-4 [doi]
- A wide range PWM signal frequency converter with the identical duty cycleJiangping He, Jiang Sun, Bo Zhang. 1-4 [doi]
- A low complexity algorithm and architecture for MIMO detection without QR decompositionLian Huai, Samer L. Hijazi, Raúl A. Casas, Gerald E. Sobelman. 1-4 [doi]
- Hybrid LED driver for multi-channel output with high consistencyD. J. Yu, Q. Yu, Ning Ning, Y. Liu, Z. Y. Shi. 1-4 [doi]
- Future low-noise technologies for RF, analog and mixed-signal integrated circuitsChih Hung Chen, Xuesong Chen, D. Y. Wu, Chao Sheng Chen. 1-4 [doi]
- A novel start-up circuit for boost DC-DC converter with synchronous power-switch current-limitYan-Ming Li, Hao Zhang, Hong Chai, Kai-Kai Wu, Chang-Bao Wen. 1-3 [doi]
- Biased MMSE soft-output detection based on conjugate gradient in massive MIMOJiangyun Zhou, JianHao Hu, Jienan Chen, Shuaining He. 1-4 [doi]
- Finite aperture time effects in sampling circuitMiho Arai, Isao Shimizu, Haruo Kobayashi, Keita Kurihara, Shu Sasaki, Shohei Shibuya, Kiichi Niitsu, Kazuyoshi Kubo. 1-4 [doi]
- TLP evaluation of ESD protection capability of graphene micro-ribbons for ICsWei Zhang, Qi Chen, Ming Xia, Rui Ma 0003, Fei Lu 0004, Chenkun Wang, Albert Z. Wang, Ya-Hong Xie. 1-4 [doi]
- A high efficiency all-PMOS charge pump for 3D NAND flash memoryLiyin Fu, Yu Wang, Qi Wang, Shiyang Yang, Yan Yang, Zongliang Huo. 1-4 [doi]
- A 1-V 5.2-5.7 GHz low noise sub-sampling phase locked loop in 0.18 μm CMOSJincheng Yang, Zhao Zhang 0004, Peng Feng, Liyuan Liu, Nanjian Wu. 1-4 [doi]
- An inclusive fault model for Network-on-ChipYi He, Gensheng Chen. 1-4 [doi]
- Realization of intelligent optimization algorithm on IP cores partition for NoC testingYunhui Ling, Fang Liu, Ying Zhang. 1-4 [doi]
- Driver circuit system for temperature control of micro-hotplates: Measurement and strategyJiarui Wu, Jun Yu 0003, Jiaming Liang, Zhan Shi, Zhongzhou Li, Zhenan Tang. 1-4 [doi]
- A 400mV supply voltage self-start clock generator for energy harvest systemYanqin Chen, Hongguang Zhang, Xu Guo, Zhiliang Hong. 1-3 [doi]
- A VLSI global placement solver based on proximal alternating direction methodJianli Chen, Zheng Peng 0002, Wenxing Zhu. 1-4 [doi]
- Survey and statistical analysis of THz detectorsXu-Guang Li, Dong Yan, Haipeng Fu, Jianguo Ma. 1-4 [doi]
- A reference-less all-digital burst-mode CDR with embedded TDCMengyin Jiang, Yuan Wang 0001, Baoguang Liu, Yuequan Liu, Song Jia, Xing Zhang 0002. 1-4 [doi]
- NBTI prediction and its induced time dependent variationJian F. Zhang, Meng Duan, Zhigang Ji, Weidong Zhang 0002. 1-4 [doi]
- A 3.5-A buck DC-DC regulator with wire drop compensation for remote-loading applicationsLei Zhu, Qi Cheng, Jianghui Deng, Jianping Guo, Dihu Chen, Xidong Ding. 1-4 [doi]
- A digitally calibrated low-power ring oscillatorMing Li, Haibin Yin, Peiyuan Wan. 1-4 [doi]
- Design and implementation of precise measuring method for the access time of embedded memoryYuqing Hu, Lijun Zhang, Youzhong Li, Qixiao Zhang, Erliang Li, Wei Jiang. 1-4 [doi]
- PS-BloTAM: Pre-sampling based architecture-level temperature analysis methodologyTian Zou, Zuying Luo. 1-4 [doi]
- Power supply noise and its reduction in at-speed scan testingXiaoqing Wen. 1-4 [doi]
- A timing failure tolerance design with in-field simultaneous error detection and correctionZiyi Hao, Xiaoyan Xiang, Chen Chen, Jianyi Meng. 1-4 [doi]
- A 10b, 0.7ps resolution coarse-fine time-to-digital converter in 65nm CMOS using a time residue amplifierJiyu Chen, Song Jia, Yuan Wang 0001. 1-4 [doi]
- An 8-bit 4fs-step digitally controlled delay element with two cascaded delay unitsWeizhen Wang, Hao Zhou, Fan Ye 0001, Junyan Ren. 1-4 [doi]
- A novel configuration context cache structure of reconfigurable systemsYu Gong, Bo Liu, Chen Mei, Rui-he Wang. 1-4 [doi]
- A lowpass/bandpass reconfigurable continuous-time ΔΣ ADC for software-defined radioXinpeng Xing, Gaozhan Cai, Georges G. E. Gielen. 1-4 [doi]
- A routing algorithm for Network-on-Chip with self-similar trafficWei Ni, Zhenwei Liu. 1-4 [doi]
- Four-bit transient-to-digital converter with a single RC-based detection circuit for system-level ESD protectionNan Han, Yuan Wang 0001, Guangyi Lu, Jian Cao, Xing Zhang 0002. 1-4 [doi]
- An iterative synthesis method for timing-driven designZhang Jie, Jin Lin. 1-3 [doi]
- Effect of field implantation on off- and on-state characteristics for thin layer SOI field P-channel LDMOSXin Zhou, Ming Qiao, Yang Li, Zhaoji Li, Bo Zhang. 1-4 [doi]
- Event-driven analog-to-digital converter for ultra low power wearable wireless biomedical sensorsZhenzhen Tian, Rendong Ying, Peilin Liu, Guoxing Wang, Yong Lian. 1-4 [doi]
- A low cost and high reliability true random number generator based on resistive random access memoryJianguo Yang, Juan Xu, Bo Wang, Xiaoyong Xue, Ryan Huang, Qingtian Zou, Jingang Wu, Yinyin Lin. 1-4 [doi]
- A 60-GHz wireless transceiver with dual-mode power amplifier for IEEE 802.11ad in 65nm CMOSBaoyong Chi, Lixue Kuang, Haikun Jia, Zhiping Wang, Zhihua Wang. 1-4 [doi]
- Design of energy efficient LDPC decoders with low-voltage strategyJianing Su, Jun Han. 1-4 [doi]
- FPGA bitstream compression and decompression based on LZ77 algorithm and BMC techniqueYuanpei Gao, Haijiang Ye, Jian Wang, Jinmei Lai. 1-4 [doi]
- Optimal design on asynchronous system with gate-level pipeliningMasato Tamura, Atsushi Ito, Makoto Ikeda. 1-4 [doi]
- The design of face recognition system based on ARM9 embedded platformFeng Ru, Xiaohong Peng, Ligang Hou, Jinhui Wang, Shuqin Geng, Chen Song. 1-4 [doi]
- Toward 5 G: An integrated CMOS wide band arbitrary waveform generator for carrier aggregationYann Deval, Yoan Veyrac, Francois Rivet. 1-4 [doi]
- A 1.8-V 12-bit self-calibrating SAR ADC with a novel comparatorChenxi Deng, Long Zhao, Hui Zheng, Yuhua Cheng. 1-4 [doi]
- A dynamic and low latency wireless NoC architectureYiou Chen, Xiang Ling, JianHao Hu. 1-3 [doi]
- A wideband VCO with constant tuning-gain and uniform sub-band interval for single-chip UHF RFID readerJianqiao Tang, Runxi Zhang, Chunqi Shi. 1-4 [doi]
- Opportunities and challenges: Ultra-low voltage digital IC design techniquesTony T. Kim, Jun Zhou, Yong Lian. 1-4 [doi]
- Low noise coupling techniques for multi-phase oscillatorsFa Foster Dai, Feng Zhao, Rong Jiang. 1-4 [doi]
- Color image enhancement using power-constraint histogram equalization for AMOLEDHu Cao, Li Tian, Jun Liu, Hui Wang, Songlin Feng. 1-4 [doi]
- A novel low-cost interface design for SystemC and SystemVerilog Co-simulationYunzhong Zhu, Tao Li, Jingpeng Guo, Haiyang Zhou, Fangfa Fu. 1-4 [doi]
- Recent progresses of STT memory design and applicationsBonan Yan, Yaojun Zhang, Enes Eken, Wujie Wen, Weisheng Zhao, Yiran Chen. 1-4 [doi]
- An asynchronous delay line TDC for ADPLL in 0.13um CMOSChunhui Li, Lei Ma, Junhui Xiang, Hao Min. 1-4 [doi]
- Development of high-voltage ESD protection devices on smart power technologies for automotive applicationsCarol Rouying Zhan, Changsoo Hong, Jean-Philippe Laine, Patrice Besse. 1-4 [doi]
- An ECC crypto engine based on binary edwards elliptic curve for low-cost RFID tag chipCheng Wu, Fan Yang, Xi Tan, Chao Wang, Feng Chen, Junyu Wang. 1-4 [doi]
- High efficiency single-inductor dual-output DC-DC converter with ZVS-PWM controlYoshiki Sunaga, Naoya Shiraishi, Koyo Asaishi, Nobukazu Tsukiji, Yasunori Kobori, Nobukazu Takai, Haruo Kobayashi. 1-4 [doi]
- Distinguishing dynamic bridging faults and transition delay faultsCheng-Hung Wu, Saint James Lee, Kuen-Jong Lee. 1-4 [doi]
- Performance analysis of on-chip bufferless router with multi-ejection portsChaochao Feng, Zhuofan Liao, Zhonghai Lu, Axel Jantsch, Zhenyu Zhao. 1-4 [doi]
- A 39 GHz-80 GHz millimeter-wave frequency doubler with low power consumption in 65nm CMOS tehnologyQian Chen, Fazhi An, Guangyao Zhou, Shunli Ma, Fan Ye 0001, Junyan Ren. 1-4 [doi]
- Design and implementation of light load energy saving current-limiting circuitTao Zhang, Jiyao Zhang. 1-4 [doi]
- A high-performance charge pump with improved static and dynamic matching characteristicHaibin Shao, Ke Lin, Bo Wang, Chen Chen, Fang Gao, Feng Huang, Xin'an Wang. 1-4 [doi]
- Function-based ESD protection circuit design verification for BGA pad-ring arrayLi Wang, Rui Ma 0003, Fei Lu 0004, Albert Z. Wang, Zongyu Dong, Xin Wang, Chen Zhang, Bin Zhao, Siqiang Fan, He Tang. 1-4 [doi]
- A full layer parallel QC-LDPC decoder for WiMAX and Wi-FiWenchao Zhang, Song Chen 0001, Xuefei Bai, Dajiang Zhou. 1-4 [doi]
- A 0.4V 53dB SNDR 250 MS/s time-based CT ΔΣ analog to digital converterHung-kai Chen, Wei-Zen Chen, Zhiyuan Ren. 1-4 [doi]
- Design of novel chopper stabilized rail-to-rail operational amplifierYong Xu, Fei Zhao, Zheng Sun, Yuanliang Wu. 1-4 [doi]
- A PVT variation tolerant and low power 5Gb/s clock and data recovery circuit for PCI-E 2.0/USB 3.0Feng Zhang 0014, Hao Ju, Chengying Chen. 1-4 [doi]
- A high reliability synchronous boost converter with spike suppression circuitJiangping He, Pengfei Liao, Bo Zhang. 1-4 [doi]
- A fully integrated 0.18 μm SiGe BiCMOS power amplifierGuoJun Liu. 1-4 [doi]
- A novel symbol synchronization algorithm and low-complexity circuits design for zero-IF GFSK demodulatorGuanghua Wu, Hong Chen, Yanyi Meng, Xitian Long, Kun Yang, Xueping Jiang. 1-4 [doi]
- EMI reduction by analog noise spread spectrum in new ripple controlled converterYasunori Kobori, Taifeng Wang, Nobukazu Tsukiji, Nobukazu Takai, Haruo Kobayashi. 1-4 [doi]
- A low power 1.5GHz Gm-C filter with 0-40dB variable gain in 65-nm CMOS technologyHaoyu Mei, Wei Li. 1-4 [doi]
- An area-efficient 10-bit two-stage DAC for active matrix organic light-emitting diodes display driversZunkai Huang, Yiling Ding, Li Tian, Qi Zhang, Hui Wang, Songlin Feng. 1-4 [doi]
- TCAD simulations of novel Interrupted-P-Finger UV/Blue photodiode based on CMOS processXiangliang Jin, Zhenyu Jiang, Manfang Tian. 1-4 [doi]
- Analysis and design of a high linearity quadrature demodulator based on SiGe BiCMOS processYadi Guo, Renyuan Chang, Jun Fu, Baoyong Chi, Yudong Wang. 1-4 [doi]
- A novel oscillator-based TRNG for smart IC cardXiaoyan Jia, Liji Wu, Beibei Wang, Xiangmin Zhang. 1-4 [doi]
- A 6b 2b/cycle SAR ADC beyond 1GS/s with hybrid DAC structure and low kickback noise comparatorsLong Zhao, Chenxi Deng, Yuhua Cheng. 1-4 [doi]
- Comparator circuits automation by combination of distributed genetic algorithm and HSPICE optimizationKento Suzuki, Nobukazu Takai, Masato Kato, Hiroaki Seki, Yoshiki Sugawara, Haruo Kobayashi. 1-4 [doi]
- Low noise design of 32-channel snapshot X-ray readout ICDan Liu, Feng Gao, Liguang Hao. 1-4 [doi]
- Nanosecond-order fast switching and ultra-multilevel storage in lateral GeTe and Ge1Sb4Te7-based phase-change memoriesYou Yin, Sumio Hosaka. 1-4 [doi]
- A distributive on-chip voltage regulation scheme for power supply in AMOLED driver ICsWeikai Jiang, Hing Mo Lam, Hui Shao, Hesheng Lin, Min Zhang. 1-4 [doi]
- Investigation of line tunnel field effect transistor with Ge/Si heterojunctionShuqin Zhang, Chunsheng Jiang, Libin Liu, Jing Wang, Jun Xu. 1-4 [doi]
- A high input impendence AC-coupled SoC suitable for wearable ExG monitorYubin Zhang, Yajie Qin, Han Jin. 1-4 [doi]
- Automatic design of doubly-terminated RC polyphase filters by using distributed genetic algorithmYoshiki Sugawara, Nobukazu Takai, Masato Kato, Hiroaki Seki, Kento Suzuki, Haruo Kobayashi. 1-4 [doi]
- A novel adaptive CMOS low-dropout regulator with 3A sink/source capabilityYan Yang, Qi Wang, Yu Wang, Liyin Fu, Zongliang Huo. 1-4 [doi]
- A wide-division-ratio 100MHz-to-5GHz multi-modulus divider chain for wide-band PLLFazhi An, Shunli Ma, Qian Chen, Guangyao Zhou, Fan Ye 0001, Junyan Ren. 1-4 [doi]
- Design of power-up and arbiter hybrid physical unclonable functions in 65nm CMOSYuejun Zhang, Pengjun Wang, Gang Li, Haoyu Qian, Xiaomin Zheng. 1-4 [doi]
- A CMOS THz-sensing system towards label-free DNA sequencingXiwei Huang, Yu Jiang 0004, Yang Shang, Hao Yu 0001, Lingling Sun. 1-4 [doi]
- A 1/2/4MHz multi-mode reconfigurable lowpass/complex bandpass CT ΣΔ modulator for short range wireless receiverGuodong Zhu, Junfeng Zhang, Yang Xu 0005, Zehong Zhang, Baoyong Chi. 1-4 [doi]
- A crosstalk avoidance scheme based on re-layout of signal TSVJiayi Hu, Qin Wang, Jian-Fei Jiang, Jing Xie, Zhigang Mao. 1-4 [doi]
- An energy-efficient microprocessor using multilevel error correction for timing error toleranceSheng Wang 0005, Xiaoyan Xiang, Chen Chen, Jianyi Meng. 1-4 [doi]
- An adaptive dynamical low-rank tensor approximation scheme for fast circuit simulationKim Batselier, Quan Chen, Ngai Wong. 1-4 [doi]
- Dual band power amplifier for handset applicationJie Jin, Xuguang Zhang, Xiaoxiao Jiang, Yiyuan Fang. 1-4 [doi]
- A GHz-level ring-counter-based multi-modulus fractional LO divider with on-the-fly tunabilityBukun Pan, Jing Jin, Jianjun Zhou. 1-4 [doi]
- A novel clock synchronizer for low-voltage clock distribution networkChong Lu, Zhikui Duan, Yi Ding, Hong-Zhou Tan. 1-4 [doi]
- Performance evaluation and influence of device parameters on threshold voltage of dual-material strained gate-all-around MOSFETYefei Zhang, Zunchao Li, Qingzhi Meng, Yunhe Guan, Dongxu Luo. 1-4 [doi]
- Sample-hold circuit and stage circuits in a traditional 12-b 80-Msample/s pipelined A/D converterXiang Jiang 0006, Jun Cheng, Liang Li, Ting Zhang, Liao Gong, Qiyun Ma. 1-4 [doi]
- An analytical series resistance model for on-chip stacked inductors with inclusion of proximity effect between stacked layersWanghui Zou, Yun Zeng. 1-4 [doi]
- The data retention improvement with 2T structure OTP on 0.18um CMOS technologyGuanyu Chen, Feng Lin, Yongliang Gao, Chunxu Li, Duowu Wen, Zhe Zhang. 1-4 [doi]
- Low-voltage CMOS DC-DC converters for energy harvesting applicationsZehua Chen, Weiyin Wang, Hei Wong. 1-4 [doi]
- An efficient layered ABV methodology for vision system on chip based on heterogeneous parallel processorsVictor Nshunguyimfura, Jie Yang 0033, Liyuan Liu, Nanjian Wu. 1-4 [doi]
- Investigation of a GaN-on-Si HEMT optimized for the 5th-generation wireless communicationHong-Fan Huang, Xiaoyong Liu, Jin-Shan Shi, Lin-Qing Zhang, Sheng-Xun Zhao, Min-Zhi Lin, Bin Wu, Peng-fei Wang. 1-4 [doi]
- A low-power soft error tolerant latch schemeSaki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa. 1-4 [doi]
- System-level modeling and analysis of third order MEMS accelerometerXiangliang Jin, Feng Zhang. 1-4 [doi]
- Automated design strategy for high performance mixed signal circuitsAkira Matsuzawa. 1-4 [doi]
- An automatic DC-Offset cancellation method and circuit for RF transceiversKen Xu, Min Cai, Xiao-Yong He, Zhijian Chen, Weiguo Zheng. 1-4 [doi]
- Research of reusability based on UVM verificationWei Ni, Jichun Zhang. 1-4 [doi]
- A programmable baseband processor for massive MIMO uplink multi-user detectionXiaoying Qiu, Leilei Miao, Runbin Shi, Zhiwei Wang, Liang Liu, Di Wu. 1-4 [doi]
- A dynamic reprogramming scheme to enhance the reliability of RRAMXiang Zhongyuan, Zhang Feng. 1-4 [doi]
- A peak power optimization scheduling algorithm for single cycle operations and multi-cycle operationsSun Qiang. 1-4 [doi]
- Study and implementation of cluster hierarchical memory system of multicore cryptographic processorJunwei Li, Zibin Dai, Wei Li, Tao Chen, Yufei Zhu. 1-4 [doi]
- A novel vision chip architecture for image recognition based on convolutional neural networkHonglong Li, Zhongxing Zhang, Jie Yang 0033, Liyuan Liu, Nanjian Wu. 1-4 [doi]
- A 30-GHz to 39-GHz mm-Wave low-power injection-locked frequency divider in 65nm CMOSGuangyao Zhou, Shunli Ma, Fazhi An, Ning Li, Fan Ye 0001, Junyan Ren. 1-4 [doi]
- A high PSR SOI current-mode bandgap referenceJunli Sheng, Bingjian Jiang, Zhangwen Tang. 1-4 [doi]
- A design of subthreshold SRAM cell based on RSCE and RNCEJiangzheng Cai, Jia Yuan, Li Ming Chen, Yong Hei. 1-4 [doi]
- A high-speed and area-efficient sign detector for three moduli set RNS {2n, 2n-1, 2n+1}Sachin Kumar, Chip-Hong Chang. 1-4 [doi]
- Data pre-emphasis based retention reliability enhance scheme for MLC NAND Flash memoriesHaozhi Ma, Zhongyi Gao, Liyang Pan, Jun Xu. 1-4 [doi]
- Novel CMOS technology compatible nonvolatile on-chip hybrid memoryZezhong Yang, Jinhui Wang, Ligang Hou, Na Gong. 1-4 [doi]
- An enhanced built-in self-repair technique for yield and reliability improvement of embedded memoriesShyue-Kung Lu, Hao-Wei Lin, Masaki Hashizume. 1-4 [doi]
- Design of a high voltage gate driver moduleLongcheng Que, Jian Lv, Simon S. Ang. 1-4 [doi]
- Smartphone-controlled electro-wetting on dielectric microfluidicsZhi Zeng, Kaidi Zhang, Wei Wang, Weijiang Xu, Jia Zhou. 1-4 [doi]
- A new method for demodulation of FSK signal with severe impulse interferenceHeyi Hu, Chun Zhang, Yongming Li 0004. 1-4 [doi]
- Motion artifact removal based on ICA for ambulatory ECG monitoringShudong Tian, Jun Han 0003, Jianwei Yang, Lijun Zhou, Xiaoyang Zeng. 1-4 [doi]
- A flexible HEVC intra mode decision hardware for 8kx4k real time encoderYanHeng Lu, Wei Cheng, Leilei Huang, Xiaoyang Zeng, Yibo Fan. 1-4 [doi]
- LVDS transmitter with optimized high power-efficiency 8: 1 MUXYuan Su, Yimin Wu, Qiang Zhang, Xuerong Zhou, Fan Ye 0001, Junyan Ren. 1-4 [doi]
- A low power TDC with 0.5ps resolution for ADPLL in 40nm CMOSXusong Liu, Lei Ma, Junhui Xiang, Na Yan, Haolv Xie, Xiaowei Cai. 1-4 [doi]
- Design consideration of uni-traveling carrier photodiode: Influence of doping profile and buffer layerYang Li, Hang Zhou, Pengfei Xu, Yujie Chen, Yanfeng Zhang, Siyuan Yu. 1-4 [doi]
- Analytical models for threshold voltage, drain induced barrier lowering effect of junctionless triple-gate FinFETsGuangxi Hu, Shuyan Hu, Jianhua Feng, Ran Liu 0001, Lingli Wang, Li-Rong Zheng. 1-4 [doi]
- Investigation on the immunity of microcontroller to electrical fast transientsChuangwei Li, Jiancheng Li, Jianfei Wu, Yu Xiao. 1-4 [doi]
- A 0.1-1.5G SDR transmitter with two-stage harmonic rejection power mixer in 65-nm CMOSBing Lyu, Yun Yin, Xiaobao Yu, Baoyong Chi. 1-4 [doi]
- DCPG: Double-control power gating technique for a 28 nm Cortex™-A9 MPCore Quad-core processorQian Liang, Jinhui Wang, Peiyuan Wan, Ligang Hou, Na Gong. 1-4 [doi]
- Performance analysis for matrix-multiplication based on an heterogeneous multi-core SoCYu-Kun Song, Rui Jiao, Duoli Zhang, Dongxue Gao. 1-4 [doi]
- FPGA logic design of SATA3.0 physical layerZong Yang, Hui Xu, Nan Li, Zhaolin Sun. 1-4 [doi]
- Design of a high parallelism high throughput HSPA+ Turbo decoderJieqiong Cheng, Qingqing Yang, Xiaofang Zhou. 1-4 [doi]
- A voltage doubling AC-DC converter with offset-controlled comparators for piezoelectric energy harvesterLianxi Liu, Wei Tu, Junchao Mu, Zhangming Zhu, Yintang Yang. 1-4 [doi]
- Dependency of current collapse on the device structure of GaN-based HEMTsXingye Zhou, Zhihong Feng, Yuanjie Lv, Xin Tan, Yuangang Wang, Guodong Gu, Xubo Song, Peng Xu, Shaobo Dun, Shujun Cai. 1-4 [doi]
- A 6-13 GHz wide-tuning-range low-phase-noise ring oscillator utilizing frequency multiplication techniqueBowen Yang, Zhijian Lu, Jianjun Zhou. 1-4 [doi]
- Research of segmented 8bit voltage-mode R-2R ladder DACWei Xu, Runxi Zhang, Chunqi Shi. 1-4 [doi]
- Algorithms based on all-digital phase-locked loop for fast-locking and spur freeWei Xu, Wei Li. 1-4 [doi]
- A low-cost SoC implementation of AES algorithm for bio-signalsZhicheng Xie, Jun Han 0003, Jianwei Yang, Lijun Zhou, Xiaoyang Zeng. 1-4 [doi]
- A novel stack package solution of AC-DC chip for high-power density adaptersJiaxing Wei, Jianfeng Wang, Ning Wang, Siyang Liu, Weifeng Sun. 1-4 [doi]
- A programmable divider with wide division range applied in an FMCW frequency synthesizerWu Dan, Wei Li. 1-4 [doi]
- Transaction level model of HDMI transmitter based on System VerilogXiang Liang, Ligang Hou, Jinhui Wang, Chunhui Yang, Deyang Gao, Lin Zhu. 1-4 [doi]
- An automated test framework for SRAM-based FPGAXuemin Lv, Moucheng Yang, Xuegong Zhou, Lingli Wang. 1-4 [doi]
- A 1-V 2.5-ppm/°C second-order compensated bandgap referenceMeilin Wan, Zhenzhen Zhang, Kui Dai, Xuecheng Zou. 1-4 [doi]
- A 57 to 66 GHz novel six-port correlatorPeng Siew Chew, Kiat Seng Yeo, Kaixue Ma, Zhi-Hui Kong. 1-4 [doi]
- A CMOS charge pump with dual compensation amplifiers for phase-locked loops synthesizerLitong Nie, Zhigong Wang, Lu Tang, Junliang Wang, Luosi Gao. 1-4 [doi]
- Droplet generating with accurate volume for EWOD digital microfluidicsWei Wang, Jianfeng Chen, Jia Zhou. 1-4 [doi]
- Fibonacci sequence weighted SAR ADC algorithm and its DAC topologyTakuya Arafune, Yutaro Kobayashi, Shohei Shibuya, Haruo Kobayashi. 1-4 [doi]
- A configurable SoC design for information securitySizhong Xuan, Jun Han 0003, Zhiyi Yu, Yi Ren, Xiaoyang Zeng. 1-4 [doi]
- Exploration for energy-efficient ECC decoder of WBANTianchan Guan, Jun Han 0003, Xiaoyang Zeng. 1-4 [doi]
- A load-transient-enhanced output-capacitor-free low-dropout regulator based on an ultra-fast push-pull amplifierShaowei Zhen, Ji Wang, Dongjie Yang, Canhua Cao, Ping Luo. 1-4 [doi]
- High-frequency low-distortion signal generation algorithm with arbitrary waveform generatorShohei Shibuya, Yutaro Kobayashi, Haruo Kobayashi. 1-4 [doi]
- A 0.06 mm2 6 dBm IB1db wideband CMOS class-AB LNTA for SAW-less applicationsJun Chen, Benqing Guo, Boyang Zhang, Guangjun Wen. 1-4 [doi]
- Elliptic curve GF (p) point multiplier by dual arithmetic coresTao Wu. 1-4 [doi]
- A nanopower, high PSRR full CMOS voltage reference circuit consisting of subthreshold MOSFETsJian Li, Jiancheng Li, Li Yang. 1-4 [doi]
- A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technologyFangxu Lv, Xuqiang Zheng, Ziqiang Wang, Jianye Wang, Fule Li. 1-4 [doi]
- DPALS: A dynamic programming-based algorithm for two-level approximate logic synthesisChen Zou, Weikang Qian, Jie Han. 1-4 [doi]
- Influence of nitrogen buffering on oxygen in indium-tin-oxide capped resistive random access memory with NH3 treatmentJi Chen, Jen-Chung Lou, Kuan-Chang Chang, Ting-Chang Chang, Tsung-Ming Tsai, Chih-Hung Pan. 1-4 [doi]
- A 14-bit 2-GS/s DAC with a programmable interpolation filterFeng Ye, Haijun Wang, Ting Yi, Zhiliang Hong. 1-4 [doi]
- System-level design solutions: Enabling the IoT explosionLiwei Yang, Yao Chen, Wei Zuo, Tan Nguyen, Swathi T. Gurumani, Kyle Rupnow, Deming Chen. 1-4 [doi]
- 10 Mbps high-voltage digital transciever on single die for 50 V voltage swingChua-Chin Wang, Min-Yu Tseng. 1-4 [doi]
- A 1.5-GS/s 5-bit interpolating ADC with offset averaging and interpolating sharing resistors networkRongjin Xu, Yongzhen Chen, Mingshuo Wang, Ning Li, Fan Ye 0001, Junyan Ren. 1-4 [doi]
- A new reading scheme for multitime programmable (MTP) memory cellsCong Li, Jiancheng Li, Wenxiao Li, Shunqiang Xu, Yaling Chen. 1-4 [doi]
- Fabrication of 3.1kV/10A 4H-SiC Junction Barrier Schottky DiodesChengsen Wang, Hao Yuan, Qingwen Song, XiaoYan Tang, Renxu Jia, YuMing Zhang, YiMen Zhang, Yidong Shen. 1-3 [doi]
- A lifting-based 2-D discrete wavelet transform architecture for data compression of bio-potential signalsYi Ren, Jun Han 0003, Zhiyi Yu, Sizhong Xuan, Xiaoyang Zeng. 1-4 [doi]
- Split-based 200Msps and 12 bit ADC designHaiJun Lin, Xiao Yang. 1-4 [doi]
- An improved voltage bandgap reference with high-order curvature compensationNan Lyu, Ning Mei Yu, Min Yi. 1-4 [doi]
- Self-recovering short-circuit protection circuit for RF class-D power amplifierZheng Sun, Wei Ding, Yong Xu, Ying Huang, Guangyan Ma, Yuanliang Wu. 1-4 [doi]
- High-speed realization of trivium based on multi-core cryptographic processorZhou Chuang Wang, Zi Bin Dai. 1-4 [doi]
- Circuit design techniques for multimedia wireline communicationsChulwoo Kim. 1-4 [doi]
- Overshoot stress impact on HfO2 high-κ layer dynamic SILCGuangxing Wan, Tianli Duan, Shuxiang Zhang, Lingli Jiang, Bo Tang, Chao Zhao, Huilong Zhu, Hongyu Yu. 1-4 [doi]
- A TSV alignment design for multilayer 3D ICWei Zhao, Ligang Hou, Xiaohong Peng, Jinhui Wang, Jingyan Fu, Yang Yang. 1-4 [doi]
- A SRAM-saving two-stage storage strategy for the coefficients memories in HEVC encodersLeilei Huang, Wei Cheng, Xiaoyang Zeng, Yibo Fan. 1-4 [doi]
- Novel superjunction collector design of power SiGe HBTs for high fT×BVCEO×β productXiao Wang, Dongyue Jin, Wanrong Zhang, Xinyi Zhao, Yanling Guo, Qiang Fu. 1-4 [doi]
- Spin orbit torques for ultra-low power computingKaihua Cao, Heng Zhao, Mengxing Wang, Weisheng Zhao. 1-4 [doi]
- Design of low-power FinFET-based TCAMs with unevenly-segmented matchlines for routing table applicationsMeng-chou Chang, Kai-Lun He. 1-4 [doi]
- A DPA resistant dual rail Préchargé logic cellXiao Pang, Jing Wang, Chenxu Wang, Xinsheng Wang. 1-4 [doi]
- Selectable notch frequencies of EMI spread spectrum using pulse modulation in switching converterYasunori Kobori, Takuya Arafune, Nobukazu Tsukiji, Nobukazu Takai, Haruo Kobayashi. 1-4 [doi]
- Advanced germanium channel transistors (invited)C. W. Liu, I.-H. Wong, S. H. Huang, C. H. Huang, S. H. Hsu. 1-4 [doi]
- Comprehensive study on higher order radix RSA cryptography engineTukasa Ikeda, Makoto Ikeda. 1-4 [doi]
- A high-sensitivity ASK demodulator for passive UHF RFID tags with automatic voltage limitation and average voltage detectionLi Yang, Jiancheng Li, Minghua Tang, Lei Cai, Jian Li, Miaoxia Zheng. 1-4 [doi]
- A reconfigurable analog baseband for low-power Wi-Fi receiverJiachen Hao, Zheng Song, Baoyong Chi. 1-4 [doi]
- Using GIDL mechanism for low-power consumption and data retention time improvement in a double-gate nanowire TFT 1T-DRAM with Fin-Gate and Pillar-Body structureWei-Han Lee, Jyi-Tsong Lin, Yu-Chun Wang, Po-Hsieh Lin, Chien-Chia Lai, Yong-Huang Lin, Tin-Chun Chang. 1-4 [doi]
- Hardware security applications of emerging nonvolatile memoriesAn Chen. 1-4 [doi]
- A power efficient current-mode differential driver for FPGAsYuanlong Xiao, Jian Wang, Jinmei Lai. 1-4 [doi]
- A novel direct digital frequency synthesizer employing complementary dual-phase latch-based architectureAbdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa. 1-4 [doi]
- Low voltage adaptive delay clock buffer designYafei Liu, Xiangyu Li. 1-4 [doi]
- A novel SCR-LDMOS for high voltage ESD protectionJing Deng, Xingbi Chen. 1-4 [doi]
- Network-coding-based distributed relay scheme for PLC networksJiaan Dai, Xiaofang Zhou, Linshan Zhang, Gerald E. Sobelman. 1-4 [doi]
- Humidity sensor with graphene oxide as sensing materialXiaoxu Kang, Qingyun Zuo, Chao Yuan, Weijun Wang, Meng Gao, Liangliang Jiang, Yongxing Zhou, Yong Wang, Shoumian Chen, Yuhang Zhao, Jia Liu, Wenjie Sheng, Jia Zhou. 1-3 [doi]
- An FPGA acceleration system of exact helical CBCT image reconstructionYan Zhang, Qi Fang, Robert K. F. Teng, Lun Gao. 1-4 [doi]
- Design and implementation of a MAC protocol for a wearable monitoring system on human bodyNing Li, Ke Lin, Shanshan Yong, Xiaofei Chen, Xinan Wang, Xing Zhang. 1-4 [doi]
- Study on maximum electric field modeling used for HCI induced degradation characteristic of LDMOS transistorsMasashi Higashino, Hitoshi Aoki, Nobukazu Tsukiji, Masaki Kazumi, Takuya Totsuka, Haruo Kobayashi. 1-4 [doi]
- Investigation of self-heating effect in SOI tunnel field-effect transistorC. Qian, Mao-Lin Shi, Lin Chen, Q. Q. Sun, Peng Zhou, S. J. Ding, D. W. Zhang. 1-4 [doi]
- A calibration technique for SAR ADC based on code density testXian Gu, XiuJu He, Fule Li. 1-4 [doi]
- Lagrangian relaxation based topology synthesis for Application-Specific Network-on-ChipsJinglei Huang, Zhigang Li, Wei Zhong, Song Chen 0001. 1-4 [doi]
- A low-power continuous-time comparator with enhanced bias current at the flip pointHongyi Wang, Yanjiao Du, Xu Jia, Youyou Fan. 1-4 [doi]
- Development of TFET 0.13 μm standard cell library for ultra-low power applicationsFang Gao, Jipan Huang, Hongying Chen, Xin'an Wang. 1-4 [doi]
- Small-sized and noise-reducing power analyzer design for low-power IoT devicesRyosuke Kitayama, Takashi Takenaka, Masao Yanagisawa, Nozomu Togawa. 1-4 [doi]
- Fault detection and redundancy design for TSVs in 3D ICsSai Hu, Qin Wang, Zheng Guo 0001, Jing Xie, Zhigang Mao. 1-4 [doi]
- Circuits and systems for 5G network: Massive MIMO and advanced codingLiang Liu, Chuan Zhang. 1-4 [doi]
- A novel routing structure of coarse-grained reconfigurable architecture for radar applicationBo Liu, Dongming Zhang, Wei-qi Ge, Yu Gong. 1-4 [doi]
- Full-digital high throughput design of adaptive decision feedback equalizers using coefficient-lookaheadWen-Quan He, Yu-Chun Lin, Jui-Yi Hung, Shyh-Jye Jou. 1-4 [doi]
- A 16-channel electrode driver with precise calibration for electrical neural stimulationChao Peng, Jinyong Zhang, Xu Zhang, Lei Wang. 1-4 [doi]
- A novel power optimization mechanism for pipelined ADCsXiaojin Fu, He Tang. 1-4 [doi]
- A study on HCI induced gate leakage current model used for reliability simulations in 90nm n-MOSFETsNobukazu Tsukiji, Hitoshi Aoki, Masaki Kazumi, Takuya Totsuka, Masashi Higashino, Haruo Kobayashi. 1-4 [doi]
- SPICE model for dual-extended memristorZhiyuan Li, Qingkun Li, Dianzhong Wen. 1-4 [doi]
- An effective analytical 3D placer in monolithic 3D IC designsYande Jiang, Xu He, Chang Liu 0019, Yang Guo. 1-4 [doi]
- A dual-band frequency tunable complex filter with stable quality-factor in different temperaturesSuoping Hu, Dongpo Chen, Tingting Mo. 1-4 [doi]
- Challenges and future trends for embedded security in electric vehicular communicationsYi Wang, Zhiqian Hong, Jun Li, Shaobo Luo, Yajun Ha. 1-4 [doi]
- A 0.3V-to-1.1V standard cell library in 40nm CMOSJintao Li, Ming Liu 0015, Hong Chen 0002, Zhihua Wang. 1-4 [doi]
- Design of a novel high-accuracy LED driving chipGuangfa Si, Yong-Sheng Yin, Honghui Deng. 1-4 [doi]
- A deterministic optimal task migration algorithm design in NoC-based multi-core systemFangfa Fu, Jun Liao, Tao Li, Jinxiang Wang. 1-4 [doi]
- A simple semi-analytical parameter extraction method for 40nm gatelength MOSFETPanpan Yu, Ying Zhou, Ling Sun, Jianjun Gao. 1-4 [doi]
- A low voltage SRAM sense amplifier with offset cancelling using digitized multiple body biasingBingyan Liu, Yong Hei. 1-4 [doi]
- Multi-technology simulation with mixed design environmentsBin Wan, Cindy Zhang, Xingang Wang. 1-4 [doi]
- An improved FFT architecture optimized for reconfigurable application specified processorFeng Han, Li Li, Kun Wang, Fan Feng, Hongbing Pan, Dong Yu. 1-4 [doi]
- The compact Vth model for biaxial strained Si NMOSFETShujuan Yin. 1-4 [doi]
- A near threshold error resilient processor based on dynamic timing error prediction and within-a-cycle timing error correctionTao-Tao Zhu, Xiaoyan Xiang, Chen Chen, Jianyi Meng. 1-4 [doi]
- Reliability concerns on time-to-digital converter due to bias temperature instability in nanometer eraXinsheng Wang, Lifeng Shang, Heyi Yin. 1-4 [doi]
- A low power and high speed CAM design using pulsed voltage for search-lineSong Jia, Weiting Li, Wenyi Tang, Yuan Wang 0001. 1-4 [doi]
- Energy-efficient sub-threshold level shifterLiang Wen, Li Li 0038, Haibo Wen, Xiaoyang Zeng. 1-4 [doi]
- Post-bond test for TSVs using voltage divisionBingqiang Jing, Xiaole Cui, Yalin Ran, Yufeng Jin. 1-4 [doi]
- A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applicationsNan Liao, Xiaoxin Cui, Tian Wang, Kai Liao, Yewen Ni, Dunshan Yu, Xiaole Cui. 1-4 [doi]
- A high performance parallel VLSI design of matrix inversionKun Wang 0005, Li Li 0003, Feng Han, Hongbing Pan, Fan Feng, Xiao Yu. 1-4 [doi]
- A simulation analysis of back gate effects for FDSOI devicesYudong Li, Bo Tang, Jiang Yan. 1-4 [doi]
- A 100M-1.5 GHz harmonic-rejection SDR receiver front-endFeng Ma, Xin-Wang Zhang, Baoyong Chi. 1-4 [doi]
- New design for low complexity and low power partial programmable shiftersYujia Wang, Jiajia Chen 0002. 1-4 [doi]
- Design of the 1.0V bandgap reference on chipHui Shi, Zheng Sun, Yong Xu, Cheng Hu, Shan Luo, Wei Ding. 1-4 [doi]
- Noise analysis of a CDS circuit with offset cancelingXiao Wang 0005, Zelin Shi, Baoshu Xu. 1-4 [doi]
- A countermeasure for power analysis to scalar multiplication of ECC hardwareLifei Liu, Xiaole Cui, Yalin Ran, Xiaoxin Cui. 1-4 [doi]
- Lateral asynchronous and vertical synchronous 3D Network on Chip with double pumped vertical linksYuxiang Fu, Li Li, Yuang Zhang, Hongbing Pan, Feng Han, Kun Wang. 1-4 [doi]
- A high performance massive MIMO detector based on log-domain belief-propagationKaining Han, JianHao Hu, Jienan Chen, Sheng Yang. 1-4 [doi]
- A TSV repair method for clustered faultsShijie Zhang, Xiaole Cui, Qiang Zhang, Yufeng Jin. 1-4 [doi]
- Modeling and design of the LDMOSFET for RF power amplifier applicationsTing Liu, Kuan W. A. Chee. 1-4 [doi]
- Parallel implementation of AES on 2.5D multicore platform with hardware and software co-designJielin Wang, Weizhen Wang, Jianwei Yang, Zhiyi Yu, Jun Han 0003, Xiaoyang Zeng. 1-4 [doi]
- A low power potentiostat for implantable glucose sensor tagXi Tan, Sizheng Chen, Zhibin Xiao, Feng Chen, Junyu Wang. 1-4 [doi]
- Application of cellulose triacetate as biocompatible/biodegradable dielectrics in EWOD devicesLei Chao, Zhi Zeng, Kaidi Zhang, Wei Wang, Jia Zhou. 1-4 [doi]
- A 1-V 23-μW 88-dB DR Sigma-Delta ADC for high-accuracy and low-power applicationsLong Zhao, Chenxi Deng, Hongming Chen, Guan Wang, Yuhua Cheng. 1-4 [doi]
- Linearity enhancement algorithms for I-Q signal generation - DWA and self-calibration techniquesMasahiro Murakami, Haruo Kobayashi, Shaiful Nizam Bin Mohyar, Takahiro Miki, Osamu Kobayashi. 1-4 [doi]
- LC-KO: A congestion-aware and area&timing-oriented placement methodZhixiong Di, Yanlong Wang, Shuang Qiao, Qianyin Xiang, Quanyuan Feng. 1-4 [doi]
- Implementation of high performance hardware architecture of face recognition algorithm based on local binary pattern on FPGAYangjie Zhang, Wei Cao 0002, Lingli Wang. 1-4 [doi]
- Comparison of decoupling resistors and capacitors for increasing the single event upset resistance of SRAM cellsZhong-Shan Zheng, Zhen-Tao Li, Ning Qiao, Kai Zhao, Fang Yu, Jia-Jun Luo. 1-3 [doi]
- Energy-efficient and area-efficient switching scheme for SAR ADCsDongsheng Liu, Weila Lei, Yin Liu, Lun Li. 1-4 [doi]
- Coefficient adjustment matrix inversion approach and architecture for massive MIMO systemsXiao Liang, Chuan Zhang, Shugong Xu, Xiaohu You. 1-4 [doi]
- Design on multi-bit adder using sense amplifier-based pass transistor logic for near-threshold voltage operationFangyuan Dang, Yuan Wang 0001, Yuequan Liu, Song Jia, Xing Zhang 0002. 1-4 [doi]
- A high-efficient floating point coprocessor for SPARC Leon2 embedded processorChen Zhao, Kuizhi Mei, Fei Wang, Nanning Zheng. 1-4 [doi]
- Design and testing of CMOS compatible EEPROMHaibin Yin, Xiaohong Peng, Peiyuan Wan, Jinhui Wang, Ligang Hou. 1-4 [doi]
- A high-slew rate rail-to-rail operational amplifier by flipped voltage followersShu-Hang Zhang, Yu-Cheng Feng, Miin-Shyue Shiau, Qi-Ming Wan, Don-Gey Liu. 1-4 [doi]
- Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesisCong Hao, Jianmo Ni, Hui-Tong Wang, Takeshi Yoshimura. 1-4 [doi]
- Electrical Overstress (EOS): Challenges for component and system-level co-designSteven H. Voldman. 1-4 [doi]
- Clock skew estimate modeling for FPGA high-level synthesis and its applicationKoichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa. 1-4 [doi]