Jyi-Tsong Lin - researchr alias

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Viewing Publication 1 - 11 from 11

2023

Steeper Subthreshold Swing Attained in Ge-Source Inductive Tunneling FET via Epitaxial Tunnel Layer for Suppressed Point TunnelingYen-Chen Chang, Wei Heng Tai, Jyi-Tsong Lin. asicon 2023: 1-4 [doi]

A Simple New Line-Tunneling iTFET with Overlapping Between Gate and Source ContactJyi-Tsong Lin, Kuan-Pin Lin. asicon 2023: 1-4 [doi]

An iTFET with Control Gate for Low Power Applications in RF and Digital CircuitsHo-Hin Tse, Zheng-Hong Zhong, Jyi-Tsong Lin. asicon 2023: 1-4 [doi]

2020

Performances Improvement of Tunneling Field-Effect Transistors' with the Advanced Double-Gate PN ConstructionYu-Jen Chen, Jyi-Tsong Lin. icce-tw 2020: 1-2 [doi]

2018

Emerging FETs for Low Power and High Speed Embedded Dynamic Random Access MemoryMd. Hasan Raza Ansari, Nupur Navlakha, Jyi-Tsong Lin, Abhinav Kranti. vlsid 2018: 422-427 [doi]

2017

Threshold-voltage variability analysis and modeling for junctionless double-gate transistorsChun-Yu Chen, Jyi-Tsong Lin, Meng-Hsueh Chiang. mr, 74:22-26, 2017. [doi]

2015

Using GIDL mechanism for low-power consumption and data retention time improvement in a double-gate nanowire TFT 1T-DRAM with Fin-Gate and Pillar-Body structureWei-Han Lee, Jyi-Tsong Lin, Yu-Chun Wang, Po-Hsieh Lin, Chien-Chia Lai, Yong-Huang Lin, Tin-Chun Chang. asicon 2015: 1-4 [doi]

2011

A unipolar-CMOS with recessed source/drain loadJyi-Tsong Lin, Hsuan-Hsu Chen, Kuan-Yu Lu, Chih-Hung Sun, Tung-Yen Lai, Fu-Liang Yang. asicon 2011: 543-546 [doi]

2008

Analysis of Block Oxide Height Variations for a 40nm Gate Length bFDSOI-FETJyi-Tsong Lin, Yi-Chuen Eng. jcp, 3(5):41-45, 2008. [doi]

2007

Analysis of Si-body thickness variation for a new 40 nm gate length bFDSOIJyi-Tsong Lin, Yi-Chuen Eng, Tai-Yi Lee, Kao-Cheng Lin. vlsid 2007: 653-656 [doi]

2006

A New 1T DRAM Cell With Enhanced Floating Body EfJyi-Tsong Lin, Mike Chang. mtdt 2006: 23-27 [doi]

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