Wei-Han Lee, Jyi-Tsong Lin, Yu-Chun Wang, Po-Hsieh Lin, Chien-Chia Lai, Yong-Huang Lin, Tin-Chun Chang. Using GIDL mechanism for low-power consumption and data retention time improvement in a double-gate nanowire TFT 1T-DRAM with Fin-Gate and Pillar-Body structure. In 2015 IEEE 11th International Conference on ASIC, ASICON 2015, Chengdu, China, November 3-6, 2015. pages 1-4, IEEE, 2015. [doi]
Abstract is missing.