Polynomial-Time Formal Verification of Adder Circuits for Multiple-Valued Logic - researchr publication authors

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Philipp Niemann 0001, Rolf Drechsler. Polynomial-Time Formal Verification of Adder Circuits for Multiple-Valued Logic. In 52nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2022, Dallas, TX, USA, May 18-20, 2022. pages 9-14, IEEE, 2022. [doi]

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