Anagha Nimbekar, Chandrasekhara Srinivas Vatti, Y. V. Sai Dinesh, Sunidhi Singh, Tarun Gupta, Ramesh Reddy Chandrapu, Amit Acharyya. Low Complexity Reconfigurable-Scalable Architecture Design Methodology for Deep Neural Network Inference Accelerator. In Sakir Sezer, Thomas Büchner, Jürgen Becker 0001, Andrew Marshall, Fahad Siddiqui 0001, Tanja Harbaum, Kieran McLaughlin, editors, 35th IEEE International System-on-Chip Conference, SOCC 2022, Belfast, United Kingdom, September 5-8, 2022. pages 1-6, IEEE, 2022. [doi]
@inproceedings{NimbekarVDSGCA22,
title = {Low Complexity Reconfigurable-Scalable Architecture Design Methodology for Deep Neural Network Inference Accelerator},
author = {Anagha Nimbekar and Chandrasekhara Srinivas Vatti and Y. V. Sai Dinesh and Sunidhi Singh and Tarun Gupta and Ramesh Reddy Chandrapu and Amit Acharyya},
year = {2022},
doi = {10.1109/SOCC56010.2022.9908073},
url = {https://doi.org/10.1109/SOCC56010.2022.9908073},
researchr = {https://researchr.org/publication/NimbekarVDSGCA22},
cites = {0},
citedby = {0},
pages = {1-6},
booktitle = {35th IEEE International System-on-Chip Conference, SOCC 2022, Belfast, United Kingdom, September 5-8, 2022},
editor = {Sakir Sezer and Thomas Büchner and Jürgen Becker 0001 and Andrew Marshall and Fahad Siddiqui 0001 and Tanja Harbaum and Kieran McLaughlin},
publisher = {IEEE},
isbn = {978-1-6654-5985-3},
}