Table of Contents

• Cardinality Constrained Portfolio Optimization on an Ising MachineMatthieu Parizy, Przemyslaw Sadowski, Nozomu Togawa. 1-6 [doi]
• CNN Implementation and Analysis on Xilinx Versal ACAP at European XFELAhmad Al-Zoubi, Gianluca Martino, Fin Hendrik Bahnsen, Jun Zhu, Holger Schlarb, Görschwin Fey. 1-6 [doi]
• Post-Processing Refinement for Semi-Global Matching Algorithm Based on Real-Time FPGAYunhao Ma, Xiwei Fang, Pingcheng Dong, Xinyu Guan, Ke Li, Lei Chen, Fengwei An. 1-5 [doi]
• Noise Analysis of CMOS Ring Oscillator-based Capacitance Measurement for Lab-on-Chip ApplicationJaved S. Gaggatur. 1-6 [doi]
• Novel Pulse Detection System Using Differentiation: Optical Experimental ResultsSharath Patil, Bhanu Singh, Raunak Borwankar, Martin Margala. 1-5 [doi]
• An Architecture for On-Chip Face Recognition in a Compressive Image SensorAmir Khan, Jorge Fernández-Berni, Ricardo Carmona-Galán. 1-6 [doi]
• A Stochastic Coding Method of EEG Signals for Sleep Stage ClassificationGuangxian Zhu, Huijia Wang, Yirong Kan, Zheng Chen 0012, Ming Huang 0002, Md. Altaf-Ul-Amin, Naoaki Ono, Shigehiko Kanaya, Renyuan Zhang, Yasuhiko Nakashima. 1-6 [doi]
• Accurate Estimation of the CNN Inference Cost for TinyML DevicesThomas Garbay, Khalil Hachicha, Petr Dobiás, Wilfried Dron, Pedro Lusich, Imane Khalis, Andrea Pinna 0001, Bertrand Granado. 1-6 [doi]
• A Scalable DC/DC Converter with Fast Load Transient Response and Security ImprovementXingye Liu, Paul Ampadu. 1-6 [doi]
• Hardware Oriented Strip-wise Optimization (HOSO) Framework for Efficient Deep Neural NetworkXiaotian Ma, Kevin Han, Yucheng Yang, Ronald F. DeMara, Yu Bai. 1-6 [doi]
• Thermal Side-channel Leakage Protection in Monolithic Three Dimensional Integrated CircuitsJaya Dofe. 1-2 [doi]
• Application and Evaluation of Quantization for Narrow Bit-width Resampling of Sequential Monte CarloHiroki Nishimoto, Renyuan Zhang, Yasuhiko Nakashima. 1-6 [doi]
• MSIM: A Highly Parallel Near-Memory Accelerator for MinHash SketchAman Sinha, Jhih-Yong Mai, Bo-Cheng Lai. 1-6 [doi]
• Securing Microservices Against Password Guess Attacks using Hardware Performance CountersSai Praveen Kadiyala, Xiaolan Li, Wonjun Lee, Andrew Catlin. 1-6 [doi]
• Virtual Platform Acceleration through Userspace Host ExecutionLukas Jünger 0001, Antonios Salios, Peter Blöcher, Rainer Leupers. 1-6 [doi]
• Design and Implementation of Stochastic Neural Networks Using Superconductor Quantum-Flux-Parametron DevicesOlivia Chen, Yanzhi Wang, Renyuan Zhang, Nobuyuki Yoshikawa. 1-6 [doi]
• Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled CircuitsJun Shiomi, Shogo Terada, Tohru Ishihara, Hidetoshi Onodera. 1-6 [doi]
• Investigating SAMV Regarding its Suitability For FPGAsFarehe Giahi, Sebastian Rachuj, Dietmar Fey. 1-6 [doi]
• Overhead-Aware Schedule Synthesis for Logical Execution Time (LET) in Automotive SystemsErjola Lalo, Andreas Sailer, Jürgen Mottok, Christian Siemers. 1-6 [doi]
• In-Network Accumulation: Extending the Role of NoC for DNN AccelerationBinayak Tiwari, Mei Yang, Xiaohang Wang 0001, Yingtao Jiang. 1-6 [doi]
• A Practical Man-in-the-Middle Attack on Deep Learning Edge Device by Sparse Light Strip Injection into Camera Data LaneWenye Liu, Weiyang He, Bowen Hu, Chip-Hong Chang. 1-6 [doi]
• Non-deterministic Quantization for mmWave Beam PredictionHaohui Jia, Na Chen, Renyuan Zhang, Minoru Okada. 1-6 [doi]
• Memristive Neural Network with Efficient In-Situ Supervised TrainingSantlal Prajaprati, Manobendra Nath Mondal, Susmita Sur-Kolay. 1-6 [doi]
• An RRAM-based Neural Radiance Field ProcessorYueyang Zheng, Chaolin Rao, Haochuan Wan, Yuliang Zhou, Pingqiang Zhou, Jingyi Yu, Xin Lou. 1-5 [doi]
• Machine Learning Based Parameter Tuning for Performance and Power optimization of Multisource Clock Tree SynthesisPrasenjit Ray, V. Sai Prashant, Bindu P. Rao. 1-2 [doi]
• Runtime Adaptive Cache Checkpointing for RISC Multi-Core ProcessorsFabian Kempf, Julian Höfer, Fabian Kreß, Tim Hotfilter, Tanja Harbaum, Jürgen Becker 0001. 1-6 [doi]
• Energy-Based Analog Neural Network FrameworkMohamed Watfa, Alberto Garcia-Ortiz, Gilles Sassatelli. 1-6 [doi]
• A Novel Combined Correlation Power Analysis (CPA) Attack on Schoolbook Polynomial Multiplication in Lattice-based CryptosystemsChuanchao Lu, Yijun Cui, Ayesha Khalid, Chongyan Gu, Chenghua Wang, Weiqiang Liu. 1-6 [doi]
• Energy-Efficient Black Hole Router Detection in Network-on-ChipLuka Daoud, Nader Rafla. 1-6 [doi]
• GAND-Nets: Training Deep Spiking Neural Networks with Ternary WeightsMan Wu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima. 1-6 [doi]
• An Efficient FPGA Accelerator for Point CloudZilun Wang, Wendong Mao, Peixiang Yang, Zhongfeng Wang, Jun Lin. 1-6 [doi]
• RECO-HCON: A High-Throughput Reconfigurable Compact ASCON Processor for Trusted IoTXiangdong Wei, Mohamed El-Hadedy 0001, Sergiu Mosanu, Zhengping Zhu, Wen-mei Hwu, Xinfei Guo. 1-6 [doi]
• Towards Hardware Trojan Resilient Design of Convolutional Neural NetworksPeiyao Sun, Basel Halak, Tomasz Kazmierski. 1-6 [doi]
• Quantum Key Distribution Post-processing: A Heterogeneous Computing PerspectiveHe Li, Adrian Wonfor, Amanda Weerasinghe, Muataz Alhussein, Yupeng Gong, Richard V. Penty. 1-6 [doi]
• A Versatile & Adjustable 400 Node CMOS Oscillator Based Ising Machine to Investigate and Optimize the Internal Computing PrincipleMarkus Graber, Klaus Hofmann. 1-6 [doi]
• DPReDO: Dynamic Partial Reconfiguration enabled Design Obfuscation for FPGA SecuritySandeep Sunkavilli, Nishanth Goud Chennagouni, Qiaoyan Yu. 1-6 [doi]
• Enhancing Adversarial Attacks on Single-Layer NVM Crossbar-Based Neural Networks with Power Consumption InformationCory E. Merkel. 1-6 [doi]
• In-depth Analysis of the Effects of Electromagnetic Fault Injection Attack on a 32-bit MCUJinteng Jiao, He Li, Yanzhao Feng, Chengdong Qian, Qiang Liu. 1-6 [doi]
• FPGA Implementation of Addition-based CORDIC-SNN With Izhikevich NeuronsUchechukwu Leo Udeji, Martin Margala. 1-6 [doi]
• I/O Constraints Optimization using Machine LearningLekshmi C, Anmol Khatri, Sourav Saha, Shivangi Gupta, Raj Yadav, Rakshit Bazaz. 1-6 [doi]
• Inconspicuous Data Augmentation Based Backdoor Attack on Deep Neural NetworksChaohui Xu, Wenye Liu, Yue Zheng, Si Wang, Chip-Hong Chang. 1-6 [doi]
• Efficient Hardware Approximation for Bit-Decomposition Based Deep Neural Network AcceleratorsTaha Soliman, Amro Eldebiky, Cecilia De la Parra, Andre Guntoro, Norbert Wehn. 1-6 [doi]
• A General Algorithm for Loop-gain and TDC-resolution Optimization in an ADPLL with a 2-bit TDC Phase detectorAbdelrahman G. Habib, Mohamed A. Dessouky. 1-6 [doi]
• Performance evaluation of High Bandwidth Memory for HPC WorkloadsAmit Kumar Kabat, Shubhang Pandey, Venkatesh Tiruchirai Gopalakrishnan. 1-6 [doi]
• Divided by Designs, United by Flow-Uniquified, modular and automated approach to improve design efficiencyPragya Laad, Olivier Rizzo. 1-2 [doi]
• Towards More Secure PUF Applications: A Low-Area Polar Decoder ImplementationClaus Kestel, Christoph Frisch, Michael Pehl, Norbert Wehn. 1-6 [doi]
• Modeling Attacks Resilient Multiple PUF-CPRNG Architecture Design MethodologyAgshare Dheeraj, Pabitra Das, Kiran Kumar A, Srisubha Kalanadhabhatta, Amit Acharyya. 1-6 [doi]
• Data-Centric Machine Learning Pipeline for Hardware VerificationHongsup Shin. 1-2 [doi]
• Cache-locality Based Adaptive Warp Scheduling for Neural Network Acceleration on GPGPUsWeiming Hu, Yi Zhou, Ying Quan, Yuanfeng Wang, Xin Lou. 1-6 [doi]
• kNN-MSDF: A Hardware Accelerator for k-Nearest Neighbors Using Most Significant Digit First ComputationSaeid Gorgin 0001, MohammadHosein Gholamrezaei, Danial Javaheri, Jeong-A. Lee. 1-6 [doi]
• A Mixed-Signal Interface Circuit for Integration of Embedded 1T1R RRAM ArraysStefan Pechmann, Amelie Hagelauer. 1-5 [doi]
• Efficient Low-bit-width Activation Function Implementations for Ultra Low Power SoCsShenghou Ma, Paul Ampadu. 1-6 [doi]
• A Duty Cycle Error Reduction with 1-point Calibration achieving 0.017UI in 7.2Gbps HBM3 DRAM Data ReadJaved S. Gaggatur. 1-6 [doi]
• A New Perspective of Inscribing Temporal Encryption on Spatial MPV Imprints for PUF DesignXiangye Wei, Liming Xiu. 1-6 [doi]
• The Case for SoC in Future Radio AstronomyOmar A. Yeste Ojeda, Nolan Denman, Stephen Wunduke. 1-2 [doi]
• Towards Automating a Software-Centered Development Process that considers Timing PropertiesRaphael Weber, Nico Adler, Thomas Wilhelm 0005, Andreas Sailer, Clemens Reichmann. 1-6 [doi]
• Monte Cimone: Paving the Road for the First Generation of RISC-V High-Performance ComputersAndrea Bartolini, Federico Ficarelli, Emanuele Parisi, Francesco Beneventi, Francesco Barchi, Daniele Gregori, Fabrizio Magugliani, Marco Cicala, Cosimo Gianfreda, Daniele Cesarini, Andrea Acquaviva, Luca Benini. 1-6 [doi]
• Low Complexity Reconfigurable-Scalable Architecture Design Methodology for Deep Neural Network Inference AcceleratorAnagha Nimbekar, Chandrasekhara Srinivas Vatti, Y. V. Sai Dinesh, Sunidhi Singh, Tarun Gupta, Ramesh Reddy Chandrapu, Amit Acharyya. 1-6 [doi]
• Implementation and Evaluation of Deep Neural Networks in Commercially Available Processing in Memory HardwarePrangon Das, Purab Ranjan Sutradhar, Mark Indovina, Sai Manoj Pudukotai Dinakarrao, Amlan Ganguly. 1-6 [doi]
• Hypervisor-Based Target Deployment Strategies for Time Predictability in Model-Based DevelopmentFlorian Schade, Tobias Dörr, Jürgen Becker 0001. 1-2 [doi]
• "High Five": Arm's first 5nm Silicon in flip-chip!Pragya Laad. 1-2 [doi]
• Automated Deep Learning Platform for Accelerated Analog Circuit DesignRahul Dutta, Ashish James, Salahuddin Raju, Yong-Joon Jeon, Chuan-Sheng Foo, Kevin Tshun Chuan Chai. 1-5 [doi]