Yasumasa Nishimura, Mitsuhiro Hamada, Hideto Hidaka, Hideyuki Ozaki, Kazuyasu Fujishima. A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode. J. Solid-State Circuits, 24(1):43-49, February 1989. [doi]
Abstract is missing.