A Novel Approximate Adder Design Methodology with Single LUT Delay for Fault-tolerant FPGA-based Systems - researchr publication authors

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Tuaha Nomani, Mujahid Mohsin. A Novel Approximate Adder Design Methodology with Single LUT Delay for Fault-tolerant FPGA-based Systems. In Second International Conference on Latest trends in Electrical Engineering and Computing Technologies, INTELLECT 2019, Karachi, Pakistan, November 13-14, 2019. pages 1-6, IEEE, 2019. [doi]

This author has not been identified. Look up 'Tuaha Nomani' in GoogleThis author has not been identified. Look up 'Mujahid Mohsin' in Google

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