Tuaha Nomani, Mujahid Mohsin. A Novel Approximate Adder Design Methodology with Single LUT Delay for Fault-tolerant FPGA-based Systems. In Second International Conference on Latest trends in Electrical Engineering and Computing Technologies, INTELLECT 2019, Karachi, Pakistan, November 13-14, 2019. pages 1-6, IEEE, 2019. [doi]
@inproceedings{NomaniM19,
title = {A Novel Approximate Adder Design Methodology with Single LUT Delay for Fault-tolerant FPGA-based Systems},
author = {Tuaha Nomani and Mujahid Mohsin},
year = {2019},
doi = {10.1109/INTELLECT47034.2019.8955460},
url = {https://doi.org/10.1109/INTELLECT47034.2019.8955460},
researchr = {https://researchr.org/publication/NomaniM19},
cites = {0},
citedby = {0},
pages = {1-6},
booktitle = {Second International Conference on Latest trends in Electrical Engineering and Computing Technologies, INTELLECT 2019, Karachi, Pakistan, November 13-14, 2019},
publisher = {IEEE},
isbn = {978-1-7281-2435-3},
}