A 300-MHz 16-b 0.5-/spl mu/m BiCMOS digital signal processor core LSI

Masahiro Nomura, Masakazu Yamashina, Junichi Goto, Toshiaki Inoue, Kazumasa Suzuki, Masato Motomura, Youichi Koseki, Benjamin S. Shih, Tadahiko Horiuchi, Nobuhisa Hamatake, Kouichi Kumagai, Tadayoshi Enomoto, Hachiro Yamada. A 300-MHz 16-b 0.5-/spl mu/m BiCMOS digital signal processor core LSI. J. Solid-State Circuits, 29(3):290-297, March 1994. [doi]

@article{NomuraYGISMKSHHKEY94,
  title = {A 300-MHz 16-b 0.5-/spl mu/m BiCMOS digital signal processor core LSI},
  author = {Masahiro Nomura and Masakazu Yamashina and Junichi Goto and Toshiaki Inoue and Kazumasa Suzuki and Masato Motomura and Youichi Koseki and Benjamin S. Shih and Tadahiko Horiuchi and Nobuhisa Hamatake and Kouichi Kumagai and Tadayoshi Enomoto and Hachiro Yamada},
  year = {1994},
  month = {March},
  doi = {10.1109/4.278350},
  url = {https://doi.org/10.1109/4.278350},
  researchr = {https://researchr.org/publication/NomuraYGISMKSHHKEY94},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {29},
  number = {3},
  pages = {290-297},
}