Logic testing with test-per-clock pattern loading and improved diagnostic abilities

Ondrej Novák, Zdenek Plíva. Logic testing with test-per-clock pattern loading and improved diagnostic abilities. In Manfred Dietrich, Ondrej Novák, editors, 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2017, Dresden, Germany, April 19-21, 2017. pages 54-59, IEEE, 2017. [doi]

@inproceedings{NovakP17,
  title = {Logic testing with test-per-clock pattern loading and improved diagnostic abilities},
  author = {Ondrej Novák and Zdenek Plíva},
  year = {2017},
  doi = {10.1109/DDECS.2017.7934586},
  url = {https://doi.org/10.1109/DDECS.2017.7934586},
  researchr = {https://researchr.org/publication/NovakP17},
  cites = {0},
  citedby = {0},
  pages = {54-59},
  booktitle = {20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2017, Dresden, Germany, April 19-21, 2017},
  editor = {Manfred Dietrich and Ondrej Novák},
  publisher = {IEEE},
  isbn = {978-1-5386-0472-4},
}