Validating an Automated Asynchronous Synthesis Environment with a Challenging Design: RISC-V

Willian Analdo Nunes, Marcos Luiggi Lemos Sartori, Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans. Validating an Automated Asynchronous Synthesis Environment with a Challenging Design: RISC-V. In 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, SBCCI 2023, Rio de Janeiro, Brazil, August 28 - Sept. 1, 2023. pages 1-6, IEEE, 2023. [doi]

Abstract

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